| a14cc8422a26 ("drm/amd/display: make function tables const") |
| 10e7fddd4aeb ("drm/amd/display: fix invalid function table override") |
| d72eb2037902 ("drm/amd/display: Separate mem input constuctors for dce 112 and 120") |
| 3722c794641f ("drm/amd/display: Implementing new bandwidth registers for DCE120") |
| 08b168862042 ("drm/amd/display: Move DCHUBBUB block from MemInput to HW sequencer.") |
| 516666318fe1 ("drm/amd/display: support for updated register headers on DCN") |
| 2b13d7d380d5 ("drm/amd/display: mpo debug sanity checks") |
| 6d244be884d2 ("drm/amd/display: plumbing to allow easy print of HW state for DTN") |
| d65359d571aa ("drm/amd/display: revert order change of HUBP and MPC disable") |
| 15e173352eea ("drm/amd/display: fix aviInfoFrame bar Info and add set_avMute") |
| 1674d35bf57b ("drm/amd/display: properly turn off unused mpc before front end programming") |
| b02c3b055fe2 ("drm/amd/display: hwseq init sequence update") |
| 71a2f23e9101 ("drm/amd/display: fix mpo exit hang") |
| 38917a1eb274 ("drm/amd/display: ensure OTG is locked before proceeding") |
| d21becbe0225 ("drm/amd/display: avoid disabling opp clk before hubp is blanked.") |
| 189f73e32e9a ("drm/amd/display: change order of HUBP and MPC disable according to HW guide") |
| 4fac6da2cb93 ("drm/amd/display: minor dcn10_hwseq clean up/refactor") |
| 184debdbd80b ("drm/amd/display: refactor dcn10 hw_sequencer to new reg access style") |
| 13066f9f6480 ("drm/amd/display: Rename DCN opp specific function prefixes to oppn10") |
| db3bc05034a4 ("drm/amd/display: Rename DCN mem input specific function prefixes to min.") |
| abe07e80836f ("drm/amd/display: Add DC interface for custom CSC matrix") |
| cfe4645e17f8 ("drm/amd/display: fix dcn pipe reset sequence") |
| 7950f0f9815a ("drm/amd/display: fix dc_post_update_surfaces_to_stream") |
| 70470154104e ("drm/amd/display: Get rid of seperate flip function.") |
| 7f5c22d16523 ("drm/amd/display: RV stereo support") |
| ad32734699da ("drm/amd/display: w/a for ycbcr output pre-multiplied alpha corruption") |
| f0558542a72e ("drm/amd/display: redesign mpc") |
| 4c6e75989e8e ("drm/amd/display: disable dcc when reset front end.") |
| 9edba5574d82 ("drm/amd/display: RV stereo support") |
| c9742685c24a ("drm/amd/display: add bw logging for dcn") |
| 11589813e6df ("drm/amd/display: fix enable_optc_clock reg_wait timeouts") |
| 2f1e8efd1031 ("drm/amd/display: Use surface update inuse for pending check.") |
| ba326a9185f1 ("drm/amd/display: propagate surface alpha setting from OS to DC") |
| 1bf56e62cc4f ("drm/amd/display: Call program_gamut explicitly instead of entire set_plane") |
| 1a2c82a2f161 ("drm/amd/display: fix mpc alpha programming") |
| 8eee20139a63 ("drm/amd/display: disable forced stutter disable after programming watermark") |
| 1e25ed30796b ("drm/amd/display: remove disable_clk_gate debug flag for DCN") |
| dcf6c1456ef5 ("drm/amd/display: clean up mpc programing during fe reset") |
| 5970f2aecc55 ("drm/amd/display: Enable DCN clock gating") |
| 0f9a536fe036 ("drm/amd/display: fix mpo + split pipe aquisition failure") |
| c1473558e617 ("drm/amd/display: program scaler not called.") |
| d9e8887860c9 ("drm/amd/display: fix flip register write sequence") |
| 89c872e595c4 ("drm/amd/display: fix YUV surface address programming sequence") |
| 5aff86c1b325 ("drm/amd/display: Implement input gamma LUT") |
| 98489c026edc ("drm/amd/display: Refactor use_lut() from dce110 to dce") |
| 3379da831b40 ("drm/amd/display: Use dc_update_surfaces_for_stream for flip.") |
| c34892144d38 ("drm/amd/display: dce 8 - 12 mem_input refactor to new style") |
| 4b28b76bfe14 ("drm/amd/display: fix mpo blanking out on one of planes being set not visible") |
| 81e2b2de3d9e ("drm/amd/display: add explanation for surface_update_type") |
| 86006a7f54c7 ("drm/amd/display: fix scaling calculation for proper surface input format") |
