| c2437b1f16d9 ("drm/amd/display: Expose bunch of functions from dcn10_hw_sequencer") |
| 6b8e1eb7c6e0 ("drm/amd/display: Update HW sequencer initialization") |
| 3ba43a59927f ("drm/amd/display: underflow/blankscreen recovery") |
| 34cb6b3860a4 ("drm/amd/display: compact the rq/dlg/ttu log") |
| a47654633596 ("drm/amd/display: add calculated clock logging to DTN") |
| 0a93dc7f595f ("drm/amd/display: add rq/dlg/ttu to dtn log") |
| 5ebfb7a5996e ("drm/amd/display: Move DCC support functions into dchubbub") |
| a052a516de4c ("drm/amd/display: align dtn logs and add mpc idle bit print") |
| dfd01f299987 ("drm/amd/display: add mpc to dtn log") |
| a4056c2a6344 ("drm/amd/display: use HW hdr mult for brightness boost") |
| 8ff15a8fcc58 ("drm/amd/display: Update DCN OPTC registers") |
| cf5e4a67f410 ("drm/amd/display: Add debug flag for p010_mpo_support") |
| a771c1f28921 ("drm/amd/display: Force full update on pixel_format_change") |
| 7c357e61e21b ("drm/amd/display: dpms off mute az audio endpoint only.") |
| 3be1406a72b0 ("drm/amd/display: Add timing generator count to resource pool.") |
| f8e413bf3c47 ("drm/amd/display: Move dpp reg access from hwss to dpp module.") |
| 405c50a07d3f ("drm/amd/display: Fix check for setting input TF") |
| e07f541f50a3 ("drm/amd/display: Use real BE and FE index to program regs.") |
| c8242b9858ae ("drm/amd/display: Move hubp reg access from hwss to hubp module.") |
| 72d520d4fa76 ("drm/amd/display: Update FMT and OPPBUF functions") |
| e7899002cf20 ("drm/amd/display: Fix unused variable warnings.") |
| b51adc77e220 ("drm/amd/display: Only blank DCN when we have set_blank implementation") |
| 39f26499c6ff ("drm/amd/display: Put dcn_mi_registers with other structs") |
| 4b8240bf916f ("drm/amd/display: hubp refactor") |
| e9be38b42ace ("drm/amd/display: Clean up DCN cursor code") |
| 36192e7e5703 ("drm/amd/display: Update HUBP") |
| f23d558466cf ("drm/amd/display: Move OPP mpc tree initialization to hw_init") |
| 40e045a9733f ("drm/amd/display: OPTC cleanup/implementation") |
| cc55b1f5c31a ("drm/amd/display: Set mpcc_disconnect_pending during MPC reset") |
| 16a29dd3bb18 ("drm/amd/display: Refine update flags usage in update_dchubp_dpp") |
| f7f36c1f5477 ("drm/amd/display: OPP DPG test pattern") |
| 4e1c1875c79b ("drm/amd/display: Reset MPCC muxes during init") |
| 9a0beb3944f2 ("drm/amd/display: CNVC pseudocode review follow up") |
| 5cc2687c13ee ("drm/amd/display: Implement work around for optc underflow.") |
| 1ccda80ff454 ("drm/amd/display: Use same wait mpcc idle function.") |
| feb4a3cd8eb0 ("drm/amd/display: Integrating MPC pseudocode") |
| 621fd3e39fc0 ("drm/amd/display: Set OPP default values in init_hw") |
| 8980aa3c9ed6 ("drm/amd/display: Only program watermark for full update.") |
| 4a43586bac9a ("drm/amd/display: update output csc matrix values") |
| 675634c5aba3 ("drm/amd/display: Only update output transfer function for full type.") |
| 125d10a23347 ("drm/amd/display: fix opp header register define") |
| 480bd0cf450b ("drm/amd/display: Update dchub and dpp as per update flags.") |
| afbeb2638b0a ("drm/amd/display: call set_mpc_output_csc from hwsequencer") |
| 671b00e26c6c ("drm/amd/display: Fix use before initialize warning") |
| a4e6d14ebe80 ("drm/amd/display: Optimize front end programming.") |
| e994340bfa57 ("drm/amd/display: Added Opp and Diags Interface for P to I") |
| 19ec320e82c6 ("drm/amd/display: Add update flags in to determine surface update type") |
| 9f89df7d9bdf ("drm/amd/display: Remove legacy unused workaround") |
| b8fce2c9d773 ("drm/amd/display: Optimize programming front end") |
| 7f914a62c94f ("drm/amd/display: Apply work around for stutter.") |
