| dd57602efbce ("drm/i915: Switch fbc over to for_each_new_intel_plane_in_state()") |
| 7b510451c896 ("drm/i915: Eliminate obj->state usage in g4x/vlv/chv wm computation") |
| d3a8fb3223a7 ("drm/i915: Pass the crtc state explicitly to intel_pipe_update_start/end()") |
| d305e0614601 ("drm/i915: Track minimum acceptable cdclk instead of "minimum dotclock"") |
| 8b5d27b911d7 ("drm/i915: Remove intel_flip_work infrastructure") |
| fd3a40242e87 ("drm/i915: Rip out legacy page_flip completion/irq handling") |
| bca2bf2a8f1d ("drm/i915: s/INTEL_INFO(dev_priv)->gen/INTEL_GEN(dev_priv) in i915_irq") |
| ce87ea15ebc6 ("drm/i915: Unbreak gpu reset vs. modeset locking") |
| afa8ce5b3080 ("drm/i915: Nuke legacy flip queueing code") |
| d1999e9ef84f ("drm/i915/cnl: Allow dynamic cdclk changes on CNL") |
| d8d4a512a6ff ("drm/i915/cnl: Implement CNL display init/unit sequence") |
| ef4f7a689ac5 ("drm/i915/cnl: Implement .set_cdclk() for CNL") |
| 945f2672ccbb ("drm/i915/cnl: Implement .get_display_clock_speed() for CNL") |
| ec1b4ee2834e ("drm/i915: Workaround VLV/CHV DSI scanline counter hardware fail") |
| 282dbf9b017b ("drm/i915: Pass intel_plane and intel_crtc to plane hooks") |
| ab33081a1880 ("drm/i915: Add support for sprites on g4x") |
| 04548cbada77 ("drm/i915: Two stage watermarks for g4x") |
| 42f4ac66c535 ("drm/i915: Apply the g4x TLB miss w/a to SR watermarks as well") |
| baf69ca8a51c ("drm/i915: Refactor wm calculations") |
| 0f95ff8505b2 ("drm/i915: Refactor the g4x TLB miss w/a to a helper") |
| 624a0ac32d88 ("drm/i915: Fix the g4x watermark TLB miss workaround") |
| 99834b1487c2 ("drm/i915: Fix cursor 'cpp' in watermark calculatins for old platforms") |
| 6d5019b68197 ("drm/i915: s/vlv_num_wm_levels/intel_wm_num_levels/") |
| 77d14ee415b8 ("drm/i915: s/vlv_plane_wm_compute/vlv_raw_plane_wm_compute/ etc.") |
| 3396a273851c ("drm/i915: Fix system hang with EI UP masked on Haswell") |
| ebf3f19abbfd ("Merge airlied/drm-next into drm-intel-next-queued") |
