| f1195d4ec70b ("clk: renesas: rcar-gen3: Absorb cpg_sd_clock_calc_div()") |
| b953eaaeb58e ("clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate() return value") |
| b9d0b84b3db8 ("clk: renesas: rcar-gen3: Add support for RCKSEL clock selection") |
| 38c79e2899a6 ("clk: renesas: rcar-gen3: Add support for OSC EXTAL predivider") |
| 41ceeb5fef77 ("clk: renesas: rcar-gen3: Add Z2 clock divider support") |
| 3391891fa9c8 ("clk: renesas: rcar-gen3: Add Z clock divider support") |
| 9f55b17ff638 ("clk: renesas: rcar-gen3: Restore SDHI clocks during resume") |
| 696997e004d4 ("clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocks") |
| 09a7dea9d58a ("clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3") |
| 2d6f25774332 ("clk: renesas: rcar-gen3-cpg: Refactor checks for accessing the div table") |
| f317880c5b2b ("clk: renesas: rcar-gen3-cpg: Drop superfluous variable") |
| bb1953067c05 ("clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0") |
| cecbe87d7300 ("clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0") |
| 5f3a432a44b1 ("clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()") |
| 30ad3cf00e94 ("clk: renesas: rcar-gen3-cpg: Always use readl()/writel()") |
