| f432f0060f05 ("drm/amd/display: Use dcn1 Optimal Taps Get") |
| f7de96ee8b5f ("drm/amd/display: Add DCN2 DPP") |
| 0b19fdc45fef ("drm/amd/display: fix dscl_manual_ratio_init") |
| f3ba7a2fd1eb ("drm/amd/display: inline more of fixed point code") |
| eb0e515464e4 ("drm/amd/display: get rid of 32.32 unsigned fixed point") |
| 7c91bd434e57 ("drm/amd/display: add some DTN logs for input and output tf") |
| 55a01d4023ce ("drm/amd/display: Add user_regamma to color module") |
| 586f27a3c2b0 ("drm/amd/display: csc_transform to dc_csc_transform") |
| 5c6161162a55 ("drm/amd/display: Do not use os types") |
| 0c41891c81c0 ("drm/amd/display: Refactor stream encoder for HW review") |
| a052a516de4c ("drm/amd/display: align dtn logs and add mpc idle bit print") |
| dfd01f299987 ("drm/amd/display: add mpc to dtn log") |
| a4056c2a6344 ("drm/amd/display: use HW hdr mult for brightness boost") |
| 44c6f2e59ee8 ("drm/amd/display: Handle HDR use cases.") |
| 086247a4b2fb ("drm/amd/display: Use 4096 lut entries") |
| 792474b73627 ("drm/amd/display: De PQ implementation") |
| 236d0e4f6f1e ("drm/amd/display: Refactor max color lut entries into a macro.") |
| e277adc5a06c ("drm/amd/display: Hookup color management functions") |
| 303afd2dbf1b ("drm/amd/display: Implement color management") |
| ec7e6bb81491 ("drm/amd/display: Add color module's gamma helpers to Linux build") |
| 8f8372c7d177 ("drm/amd/display: Optimize regamma calculations") |
| a6e59fa8061b ("drm/amd/display: WBSCL filter init calculation fixes") |
| 3be1406a72b0 ("drm/amd/display: Add timing generator count to resource pool.") |
| 31aec354f92c ("drm/amd/display: Implement interface for CRC on CRTC") |
| f8e413bf3c47 ("drm/amd/display: Move dpp reg access from hwss to dpp module.") |
| 405c50a07d3f ("drm/amd/display: Fix check for setting input TF") |
| e07f541f50a3 ("drm/amd/display: Use real BE and FE index to program regs.") |
| c8242b9858ae ("drm/amd/display: Move hubp reg access from hwss to hubp module.") |
| 39f26499c6ff ("drm/amd/display: Put dcn_mi_registers with other structs") |
| 4b8240bf916f ("drm/amd/display: hubp refactor") |
| 36192e7e5703 ("drm/amd/display: Update HUBP") |
| aff10cfe646b ("drm/amd/display: Remove grph_object_id.c and move function to bios_parser") |
| 78b56c523495 ("drm/amd/display: use clamping rather than truncation for CM fp conversions") |
| f23d558466cf ("drm/amd/display: Move OPP mpc tree initialization to hw_init") |
| 508f60e36a42 ("drm/amd/display: Correct fixed point calculation.") |
| 79086a55defa ("drm/amd/display: Move unity TF type to predefined types") |
| 7bc6f1ca9dbe ("drm/amd/display: add assert to verify dcn_calc input validity") |
| cc55b1f5c31a ("drm/amd/display: Set mpcc_disconnect_pending during MPC reset") |
| 16a29dd3bb18 ("drm/amd/display: Refine update flags usage in update_dchubp_dpp") |
| b629596072e5 ("drm/amd/display: Build unity lut for shaper") |
| 4e1c1875c79b ("drm/amd/display: Reset MPCC muxes during init") |
| 9a0beb3944f2 ("drm/amd/display: CNVC pseudocode review follow up") |
| 5cc2687c13ee ("drm/amd/display: Implement work around for optc underflow.") |
| 1ccda80ff454 ("drm/amd/display: Use same wait mpcc idle function.") |
| feb4a3cd8eb0 ("drm/amd/display: Integrating MPC pseudocode") |
| 621fd3e39fc0 ("drm/amd/display: Set OPP default values in init_hw") |
| 4a43586bac9a ("drm/amd/display: update output csc matrix values") |
| 675634c5aba3 ("drm/amd/display: Only update output transfer function for full type.") |
| dce46c53208f ("drm/amd/display: performance profiling instrumentation") |
| 480bd0cf450b ("drm/amd/display: Update dchub and dpp as per update flags.") |
