| fbd1cec57064 ("ARC: [plat-axs103]: Set initial core pll output frequency") | |
| 0fa400cb8a90 ("ARC: [plat-axs103] refactor the DT fudging code") | |
| f6a09bace0bb ("ARC: [plat-axs103] use clk driver #2: Add core pll node to DT to manage cpu clk") | |
| 9926c29f746d ("ARC: [plat-axs103] use clk driver #1: Get rid of platform specific cpu clk setting") |