| c45fbe1bd590 ("drm/amd/sriov skip jped ip block and close pgcg flags") |
| 1b0443b11530 ("drm/amdgpu: fix coding error of mmhub pg enablement") |
| b794616d1f6c ("drm/amd/powerplay: enable athub pg") |
| 6fb176a75574 ("drm/amd/powerplay: enable MM DPM PG for sienna_cichlid (v2)") |
| 4d72dd12f086 ("drm/amdgpu: enable JPEG3.0 for Sienna_Cichlid") |
| b467c4f5b4af ("drm/amdgpu: enable JPEG3.0 PG and CG for Sienna_Cichlid") |
| b8f10585cb20 ("drm/amdgpu: enable VCN3.0 for Sienna_Cichlid") |
| e823be13dbc2 ("drm/amdgpu: enable VCN3.0 PG and CG for Sienna_Cichlid") |
| a346ef86a97f ("drm/amdgpu: add mes block to sienna_cichlid") |
| 02bb391d916a ("drm/amd/powerplay: make gfx ds can be configure for sienna_cichlid") |
| 094cdf15e995 ("drm/amdgpu/powerplay: set Thermal control for sienna_cichlid") |
| 983ab9f2842e ("drm/amd/powerplay: enable SOC Clock Deep Sleep for sienna_cichlid") |
| 15dbe18fa634 ("drm/amd/powerplay: enable Graphics Clock Deep Sleep for sienna_cichlid") |
| 62c1ea6bbab7 ("drm/amd/powerplay: enable Ultra Low Voltage for sienna_cichlid") |
| 4cd4f45b6507 ("drm/amd/powerplay: set FCLK DPM for sienna_cichlid") |
| fea905d47125 ("drm/amd/powerplay: set SOCCLK DPM for sienna_cichlid") |
| b455159c0531 ("drm/amdgpu/powerplay: add initial swSMU support for sienna_cichlid (v2)") |
| 157e72e831cb ("drm/amdgpu: add sdma ip block for sienna_cichlid (v5)") |
| 933c8a93e241 ("drm/amdgpu: add gfx ip block for sienna_cichlid (v3)") |
| 757b3af8ecb4 ("drm/amdgpu: add ih ip block for sienna_cichlid") |
| 0b3df16b5abc ("drm/amdgpu: add gmc ip block for sienna_cichlid") |
| 2e1ba10e9271 ("drm/amdgpu/soc15: add common ip block for sienna_cichlid") |
| 117910ed92b3 ("drm/amdgpu/soc15: add support for sienna_cichlid") |
| 41fb666d5ceb ("drm/amd/powerplay: remove SRIOV check in SMU11 (v2)") |
| a16be2fe1455 ("drm/amd/powerplay: skip smu_i2c_eeprom_init/fini under sriov mode") |
| fa3d49f1e904 ("drm/amd/powerplay: remove the support of vega20 from swsmu") |
