| 3c02934b24e3 ("drm/i915/tc/tgl: Implement TC cold sequences") |
| feb7e0ef5ff8 ("drm/i915/tc/icl: Implement TC cold sequences") |
| f8bb28e63a1e ("drm/i915/display: Split hsw_power_well_enable() into two") |
| 8afb292839bb ("drm/i915/display/tc: Make WARN* drm specific where drm_priv ptr is available") |
| d6e53851ecc8 ("drm/i915/display_power: use intel_de_*() functions for register access") |
| 569caa65a495 ("drm/i915/power: convert to struct drm_device macros in display/intel_display_power.c") |
| b69fa3610b15 ("drm/i915/icl: Cleanup combo PHY aux power well handlers") |
| e8ab8d669d04 ("drm/i915/ehl: Define EHL powerwells independently of ICL") |
| 3fa01d642fa7 ("drm/i915/tgl: Program BW_BUDDY registers during display init") |
| 4645e906f2d4 ("drm/i915/tgl: Enable DC3CO state in "DC Off" power well") |
| 19c79ff82b4a ("drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask") |
| 3b51be4e4061 ("drm/i915/tc: Update DP_MODE programming") |
| 27ffe6e570aa ("drm/i915/tgl: Check the UC health of tc controllers after power on") |
| 8aaf5cbda8f1 ("drm/i915/icl: Unify disable and enable phy clock gating functions") |
| 31d9ae9d7342 ("drm/i915/tgl: Finish modular FIA support on registers") |
| a6e58d9a2e04 ("drm/i915/dsb: Check DSB engine status.") |
| 061489c65ff5 ("drm/i915/dsb: single register write function for DSB.") |
| 67f3b58f3bac ("drm/i915/dsb: DSB context creation.") |
| 8a84bacba19c ("drm/i915: Align power domain names with port names") |
| 99389390fef5 ("drm/i915/tgl: Implement TGL DisplayPort training sequence") |
