| 1b86883ccb8d ("x86/bugs: Read SPEC_CTRL MSR during boot and re-use reserved bits") |
| d72f4e29e6d8 ("x86/speculation: Move firmware_restrict_branch_speculation_*() from C to CPP") |
| dd84441a7971 ("x86/speculation: Use IBRS if available before calling into firmware") |
| f208820a321f ("Revert "x86/speculation: Simplify indirect_branch_prediction_barrier()"") |
| 64e16720ea08 ("x86/speculation: Simplify indirect_branch_prediction_barrier()") |
| 2961298efe1e ("x86/cpufeatures: Clean up Spectre v2 related CPUID flags") |
| e383095c7fe8 ("x86/cpu/bugs: Make retpoline module warning conditional") |
| 20ffa1caecca ("x86/speculation: Add basic IBPB (Indirect Branch Prediction Barrier) support") |
| a5b296636453 ("x86/cpufeature: Blacklist SPEC_CTRL/PRED_CMD on early Spectre v2 microcodes") |
| 5d10cbc91d9e ("x86/cpufeatures: Add AMD feature bits for Speculation Control") |
| fc67dd70adb7 ("x86/cpufeatures: Add Intel feature bits for Speculation Control") |
| 95ca0ee86360 ("x86/cpufeatures: Add CPUID_7_EDX CPUID leaf") |
| caf7501a1b4e ("module/retpoline: Warn about missing retpoline in module") |
| 3f7d875566d8 ("x86/retpoline: Optimize inline assembler for vmexit_fill_RSB") |
| 736e80a4213e ("retpoline: Introduce start/end markers of indirect thunk") |
| 4fdec2034b75 ("x86/cpufeature: Move processor tracing out of scattered features") |
| c995efd5a740 ("x86/retpoline: Fill RSB on context switch for affected CPUs") |
| 117cc7a908c8 ("x86/retpoline: Fill return stack buffer on vmexit") |
| da285121560e ("x86/spectre: Add boot time option to select Spectre v2 mitigation") |
| 76b043848fd2 ("x86/retpoline: Add initial retpoline support") |
| 61dc0f555b5c ("x86/cpu: Implement CPU vulnerabilites sysfs functions") |
| a89f040fa34e ("x86/cpufeatures: Add X86_BUG_CPU_INSECURE") |
| 3386bc8aed82 ("x86/entry/64: Create a per-CPU SYSCALL entry trampoline") |
| 72f5e08dbba2 ("x86/entry: Remap the TSS into the CPU entry area") |
| 1a935bc3d4ea ("x86/entry: Move SYSENTER_stack to the beginning of struct tss_struct") |
| 7fb983b4dd56 ("x86/entry: Fix assumptions that the HW TSS is at the beginning of cpu_tss") |
| ef8813ab2805 ("x86/mm/fixmap: Generalize the GDT fixmap mechanism, introduce struct cpu_entry_area") |
| aaeed3aeb39c ("x86/entry/gdt: Put per-CPU GDT remaps in ascending order") |
| 33a2f1a6c4d7 ("x86/dumpstack: Add get_stack_info() support for the SYSENTER stack") |
| 1a79797b58cd ("x86/entry/64: Allocate and enable the SYSENTER stack") |
| f2dbad36c55e ("x86: Make X86_BUG_FXSAVE_LEAK detectable in CPUID on AMD") |
| f3a624e901c6 ("x86/cpufeatures: Fix various details in the feature definitions") |
| acbc845ffefd ("x86/cpufeatures: Re-tabulate the X86_FEATURE definitions") |
| 20bb83443ea7 ("x86/entry/64: Stop initializing TSS.sp0 at boot") |
| da51da189a24 ("x86/entry/64: Pass SP0 directly to load_sp0()") |
| bd7dc5a6afac ("x86/entry/32: Pull the MSR_IA32_SYSENTER_CS update code out of native_load_sp0()") |
| c128dbfa0f87 ("x86/cpufeatures: Enable new SSE/AVX/AVX512 CPU features") |
| 0b00de857a64 ("x86/cpuid: Add generic table for CPUID dependencies") |
