| 41785ce56249 ("clk: meson: meson8b: add the VPU clock trees") |
| b882964b376f ("clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2") |
| 32cd198a1a50 ("clk: meson: meson8b: use a separate clock table for Meson8m2") |
| 74e1f2521f16 ("clk: meson: meson8b: add the GPU clock tree") |
| cce433e6bc53 ("clk: meson: meson8b: use a separate clock table for Meson8") |
| 6cb57c678bb7 ("clk: meson: meson8b: add the read-only video clock trees") |
| a7d19b05ce81 ("clk: meson: meson8b: add the CPU clock post divider clocks") |
| 7dc7eeb8c087 ("clk: meson: meson8b: run from the XTAL when changing the CPU frequency") |
| 6291b8c5ac67 ("clk: meson: meson8b: register the clock controller early") |
| 87173557d2f6 ("clk: meson: clk-pll: remove od parameters") |
| 2303a9ca693e ("clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary") |
| e40c7e3cda07 ("clk: meson: clk-pll: add enable bit") |
| 7df533a7e3d2 ("clk: meson: add gen_clk") |
| cddcb20b2bb3 ("clk: meson-axg: add clocks required by pcie driver") |
| a565242eb9fc ("clk: meson: gxbb: add the video decoder clocks") |
| b8c1ddadc815 ("clk: meson: meson8b: add support for the NAND clocks") |
| 5d1c04dde0eb ("clk: meson: Drop unused local variable and add static") |
| 05f814402d61 ("clk: meson: add fdiv clock gates") |
| 513b67ac39b0 ("clk: meson: add mpll pre-divider") |
| 093c3fac4619 ("clk: meson: axg: add hifi pll clock") |
| 0a1be867b92a ("clk: meson: add ROUND_CLOSEST to the pll driver") |
| c77de0e5c95a ("clk: meson: add gp0 frac parameter for axg and gxl") |
| 8289aafa4f36 ("clk: meson: improve pll driver results with frac") |
| c178b003bfcf ("clk: meson: remove special gp0 lock loop") |
| 117863e84247 ("clk: meson: poke pll CNTL last") |
| 2eab2d7cab28 ("clk: meson: add fractional part of meson8b fixed_pll") |
| 251b6fd38bcb ("clk: meson: rework meson8b cpu clock") |
| d610b54f7700 ("clk: meson: split divider and gate part of mpll") |
| 722825dcd54b ("clk: meson: migrate plls clocks to clk_regmap") |
| 88a4e1283681 ("clk: meson: migrate the audio divider clock to clk_regmap") |
| c763e61ae8cb ("clk: meson: migrate mplls clocks to clk_regmap") |
| 2513a28c108b ("clk: meson: migrate muxes to clk_regmap") |
| f06ddd2852b3 ("clk: meson: migrate dividers to clk_regmap") |
| 7f9768a54051 ("clk: meson: migrate gates to clk_regmap") |
| 161f6e5baabd ("clk: meson: add regmap to the clock controllers") |
| 7b174c5ebe46 ("clk: meson: remove obsolete comments") |
| 14bd7b9c8d3f ("clk: meson: only one loop index is necessary in probe") |
| 332b32a23225 ("clk: meson: use devm_of_clk_add_hw_provider") |
| 323346d31d68 ("clk: meson: use dev pointer where possible") |
| 6c00e7b76021 ("clk: meson: add axg misc bit to the mpll driver") |
| 2fa9b361e500 ("clk: meson: axg: fix the od shift of the sys_pll") |
| 6b71aceceb09 ("clk: meson: axg: add the fractional part of the fixed_pll") |
| 07f45e2ecc1b ("clk: meson: gxbb: add the fractional part of the fixed_pll") |
| 3c4fe763d64d ("clk: meson: fix rate calculation of plls with a fractional part") |
| 69d92293274b ("clk: meson: add the gxl hdmi pll") |
| 7d3142e5d64a ("clk: meson: add od3 to the pll driver") |
| 4c5f67b7ea32 ("clk: meson: use the frac parameter width instead of a constant") |
| 94aa8a41f1bc ("clk: meson: remove unnecessary rounding in the pll clock") |
| 4ed98e9572ad ("clk: meson: remove useless pll rate params tables") |
| 840e1a73ccbb ("clk: meson: check pll rate param table before using it") |
