| f1e58583b9c7 ("RISC-V: Support cpu hotplug") |
| cfafe2601374 ("RISC-V: Add supported for ordered booting method using HSM") |
| 2875fe056156 ("RISC-V: Add cpu_ops and modify default booting method") |
| e011995e826f ("RISC-V: Move relocate and few other functions out of __init") |
| b9dcd9e41587 ("RISC-V: Add basic support for SBI v0.2") |
| 8446923ae4d7 ("RISC-V: Mark existing SBI as 0.1 SBI.") |
| 8ad8b72721d0 ("riscv: Add KASAN support") |
| 20d2292754e7 ("riscv: make sure the cores stay looping in .Lsecondary_park") |
| 20bda4ed62f5 ("riscv: Implement copy_thread_tls") |
| 0da310e82d3a ("riscv: gcov: enable gcov for RISC-V") |
| 6bd33e1ece52 ("riscv: add nommu support") |
| 9e80635619b5 ("riscv: clear the instruction cache and all registers when booting") |
| accb9dbc4aff ("riscv: read the hart ID from mhartid on boot") |
| fcdc65375186 ("riscv: provide native clint access for M-mode") |
| 4f9bbcefa142 ("riscv: add support for MMIO access to the timer registers") |
| 8bf90f320d9a ("riscv: implement remote sfence.i using IPIs") |
| 3320648ecc38 ("riscv: cleanup the default power off implementation") |
| 3b03ac6bbd6e ("riscv: poison SBI calls for M-mode") |
| a4c3733d32a7 ("riscv: abstract out CSR names for supervisor vs machine mode") |
| 0c3ac28931d5 ("riscv: separate MMIO functions into their own header file") |
| 86fe639a1c16 ("riscv: enter WFI in default_power_off() if SBI does not shutdown") |
| 00a5bf3a8ca3 ("RISC-V: Add PCIe I/O BAR memory mapping") |
| f307307992bf ("riscv: for C functions called only from assembly, mark with __visible") |
| 5ed881bc3afc ("riscv: add missing header file includes") |
| ffaee2728f9b ("riscv: add prototypes for assembly language functions from head.S") |
| 1e1ac1cb651a ("Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip") |
