| 1d3cc7ab2b00 ("drm/i915/tgl: Set subplatforms") |
| 7ef5ef5cdead ("drm/i915: add force_probe module parameter to replace alpha_support") |
| 917dc6b53c27 ("drm/i915: Use Engine1 instance for gen11 pm interrupts") |
| 805446c8347c ("drm/i915: Introduce concept of a sub-platform") |
| 57b1c4460dc4 ("drm/i915: Mark AML 0x87CA as ULX") |
| 897f296152c7 ("drm/i915/ehl: Add ElkhartLake platform") |
| 29f3863d33d1 ("drm/i915/ehl: Add EHL platform info and PCI IDs") |
| cbecbccaa120 ("drm/i915: Record platform specific ppGTT size in intel_device_info") |
| 37fbbd49054b ("drm/i915: Populate pipe_offsets[] & co. accurately") |
| b2ae318acdca ("drm/i915: Rename HAS_GMCH") |
| 2b34e562361f ("drm/i915/icl: Work around broken VBTs for port F detection") |
| 3d6535cbed4a ("drm/i915: Enable fastboot by default on Skylake and newer") |
| d19f958db23c ("drm/i915: Enable fastset for non-boot modesets.") |
| 3f2e9ed0b26d ("drm/i915/icl: Detect port F presence via VBT") |
| 55277e1f3107 ("drm/i915: Always try to reset the GPU on takeover") |
| 1787a98439cc ("drm/i915: drop intel_device_info_dump()") |
| a0f04cc27c50 ("drm/i915: always use INTEL_INFO() to access device info") |
| 1400cc7e0dcd ("drm/i915: pass dev_priv to intel_device_info_runtime_init()") |
| ed5eb1b78a88 ("drm/i915/reg: abstract display_mmio_offset access") |
| 0258404f9d38 ("drm/i915: start moving runtime device info to a separate struct") |
| 6faf5916e6be ("drm/i915: Remove HW semaphores for gen7 inter-engine synchronisation") |
| 167bc759e823 ("drm/i915: Restrict PSMI context load w/a to Haswell GT1") |
| f513ac76530c ("drm/i915/icl: Mind the SFC units when resetting VD or VEBox engines") |
| 57b19d55189b ("drm/i915/icl: Record the valid VDBoxes with SFC capability") |
| f3ce44a09a15 ("drm/i915: merge gen checks to use range") |
| cf819eff907a ("drm/i915: replace IS_GEN<N> with IS_GEN(..., N)") |
| 006900087727 ("drm/i915: Rename IS_GEN to IS_GEN_RANGE") |
| d15f9cdd59ba ("drm/i915/icl: Do not change reserved registers related to PSR2") |
| 517974992593 ("drm/i915: Allocate a common scratch page") |
| 452420d22d5b ("drm/i915: Fuse per-context workaround handling with the common framework") |
| 69bcdecf1af5 ("drm/i915: Move register white-listing to the common workaround framework") |
| 28d6ccce73be ("drm/i915/selftests: Add tests for GT and engine workaround verification") |
| 094304beb4e1 ("drm/i915: Verify GT workaround state after GPU init") |
| 4a15c75c4246 ("drm/i915: Introduce per-engine workarounds") |
| 25d140faaa25 ("drm/i915: Record GT workarounds in a list") |
| 3800960afe15 ("drm/i915: Complete the fences as they are cancelled due to wedging") |
| d53db442db36 ("drm/i915: Move display device info capabilities to its own struct") |
| e1bf094b3c75 ("drm/i915: Add HAS_DISPLAY() and use it") |
| b9f78d675230 ("drm/i915/selftests: Fix live_workarounds to actually do resets") |
| 8d2f6e2f2721 ("drm/i915/selftests: Extract spinner code") |
| 39e84937b5b4 ("drm/i915: Skip engine serialisation for no-op seqno reset") |
| 0e39037b3165 ("drm/i915: Cache the error string") |
| 95fd94a645f7 ("drm/i915: avoid rebuilding i915_gpu_error.o on version string updates") |
| 8f19b401a6fc ("drm/i915: Make CHICKEN_TRANS reg not depend on enum value") |
| 931f54920ba8 ("drm/i915: Make pipe/transcoder offsets not depend on enum values") |
| fb6f0b64e455 ("drm/i915: Prevent machine hang from Broxton's vtd w/a and error capture") |
| 03981c6ebec4 ("drm/i915: Disable LP3 watermarks on all SNB machines") |
| 05e0b4bf4613 ("drm/i915: remove excess line continuation backslashes") |
| cb8ef723ab81 ("drm/i915/gen9_bc: Work around DMC bug zeroing power well requests") |
| 745aa6cdee6b ("drm/i915: Fix icl workarounds whitespaces") |
