| fd38cdb81105 ("drm/i915/dg1: Add DG1 PCI IDs") |
| 123f62de419f ("drm/i915/rkl: Add RKL platform info and PCI ids") |
| 31409fff1a39 ("drm/i915: simplify prefixes on device_info") |
| 8717c6b7414f ("drm/i915/cml: Separate U series pci id from origianl list.") |
| b6a8781a447c ("drm/i915/cml: Remove unsupport PCI ID") |
| d8203d398c0d ("drm/i915: add new gen12 dgfx platform macro") |
| 613716bbe721 ("drm/i915/tgl: Add IS_TGL_REVID") |
| 9747f0c2fb9e ("drm/i915/tgl: Add TGL PCI IDs") |
| abd3a0fe040d ("drm/i915/tgl: add initial Tiger Lake definitions") |
| c3ad8d29db5e ("drm/i915: Add missing commas to the end of the subplatform ID arrays") |
| 805446c8347c ("drm/i915: Introduce concept of a sub-platform") |
| e08891a5b7e6 ("drm/i915: Remove redundant device id from IS_IRONLAKE_M macro") |
| 86d35d4e7625 ("drm/i915: Split Pineview device info into desktop and mobile") |
| 57b1c4460dc4 ("drm/i915: Mark AML 0x87CA as ULX") |
| 897f296152c7 ("drm/i915/ehl: Add ElkhartLake platform") |
| 29f3863d33d1 ("drm/i915/ehl: Add EHL platform info and PCI IDs") |
| a7b4deeb02b9 ("drm/i915/cml: Add CML PCI IDS") |
| cbecbccaa120 ("drm/i915: Record platform specific ppGTT size in intel_device_info") |
| 37fbbd49054b ("drm/i915: Populate pipe_offsets[] & co. accurately") |
| b2ae318acdca ("drm/i915: Rename HAS_GMCH") |
| 5e0f5a58b167 ("drm/i915/cfl: Adding another PCI Device ID.") |
| 2b34e562361f ("drm/i915/icl: Work around broken VBTs for port F detection") |
| 3f2e9ed0b26d ("drm/i915/icl: Detect port F presence via VBT") |
| 55277e1f3107 ("drm/i915: Always try to reset the GPU on takeover") |
| 1787a98439cc ("drm/i915: drop intel_device_info_dump()") |
| a0f04cc27c50 ("drm/i915: always use INTEL_INFO() to access device info") |
| 1400cc7e0dcd ("drm/i915: pass dev_priv to intel_device_info_runtime_init()") |
| ed5eb1b78a88 ("drm/i915/reg: abstract display_mmio_offset access") |
| 0258404f9d38 ("drm/i915: start moving runtime device info to a separate struct") |
| 6faf5916e6be ("drm/i915: Remove HW semaphores for gen7 inter-engine synchronisation") |
| 167bc759e823 ("drm/i915: Restrict PSMI context load w/a to Haswell GT1") |
| f513ac76530c ("drm/i915/icl: Mind the SFC units when resetting VD or VEBox engines") |
| 57b19d55189b ("drm/i915/icl: Record the valid VDBoxes with SFC capability") |
| f3ce44a09a15 ("drm/i915: merge gen checks to use range") |
| cf819eff907a ("drm/i915: replace IS_GEN<N> with IS_GEN(..., N)") |
| 006900087727 ("drm/i915: Rename IS_GEN to IS_GEN_RANGE") |
| d15f9cdd59ba ("drm/i915/icl: Do not change reserved registers related to PSR2") |
| 517974992593 ("drm/i915: Allocate a common scratch page") |
| 452420d22d5b ("drm/i915: Fuse per-context workaround handling with the common framework") |
| 69bcdecf1af5 ("drm/i915: Move register white-listing to the common workaround framework") |
| 28d6ccce73be ("drm/i915/selftests: Add tests for GT and engine workaround verification") |
| 094304beb4e1 ("drm/i915: Verify GT workaround state after GPU init") |
| 4a15c75c4246 ("drm/i915: Introduce per-engine workarounds") |
| 25d140faaa25 ("drm/i915: Record GT workarounds in a list") |
| 3800960afe15 ("drm/i915: Complete the fences as they are cancelled due to wedging") |
| d53db442db36 ("drm/i915: Move display device info capabilities to its own struct") |
| e1bf094b3c75 ("drm/i915: Add HAS_DISPLAY() and use it") |
| b9f78d675230 ("drm/i915/selftests: Fix live_workarounds to actually do resets") |
| 8d2f6e2f2721 ("drm/i915/selftests: Extract spinner code") |
| 39e84937b5b4 ("drm/i915: Skip engine serialisation for no-op seqno reset") |
