| 20eea462bf2f ("drm/i915/icl: Ungate ddi clocks before IO enable") |
| 949fc52af19e ("drm/i915/icl: add pll mapping for DSI") |
| 1026bea00381 ("drm/i915/icl: Ungate DSI clocks") |
| 32250c8e0ef9 ("drm/i915/icl: Gate clocks for DSI") |
| 019cec36f372 ("drm/i915/icl: Disable DSI ports") |
| 4769b598b943 ("drm/i915/icl: Put DSI link in ULPS") |
| 522cc3f717ac ("drm/i915/icl: Power down DSI panel") |
| 4e123bd3039d ("drm/i915/icl: Disable DSI transcoders") |
| d9d996b6ca43 ("drm/i915/icl: Turn OFF panel backlight") |
| 70f4f502c47e ("drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers") |
| d364dc66e2d5 ("drm/i915/icl: Configure DSI transcoders") |
| ca8fc99f2ac1 ("drm/i915/icl: Get DSI transcoder for a given port") |
| 67551a703544 ("drm/i915/dsi: abstract dphy parameter init") |
| 2bf3f59daeee ("drm/i915/dsi: refactor bitrate calculations in intel_dsi_vbt_init()") |
| 70a7b83628fa ("drm/i915/icl: Program T_INIT_MASTER registers") |
| ba3df888be90 ("drm/i915/icl: Enable DDI Buffer") |
| 3f4b9d9d02c6 ("drm/i915/icl: DSI vswing programming sequence") |
| fc41001d9708 ("drm/i915/icl: Configure lane sequencing of combo phy transmitter") |
