| b73b7f48895a ("Revert "drm/amd/display: setting the DIG_MODE to the correct value."") |
| 967a3b85bac9 ("drm/amd/display: setting the DIG_MODE to the correct value.") |
| 1a9e3d4569fc ("drm/amd/display: Set DSC before DIG front-end is connected to its back-end") |
| 606b355170b5 ("drm/amd/display: add hdmi2.1 dsc pps packet programming") |
| ec16ac6b4264 ("drm/amd/display: fix dsc disable") |
| f82c916c4197 ("drm/amd/display: add some parameters to validate bandwidth functions") |
| ba32c50f0446 ("drm/amd/display: decouple dsc adjustment out of enablement") |
| 278141f58e2c ("drm/amd/display: Use DCN2 functions instead of DCE") |
| 6936c8b1d415 ("drm/amd/display: DCN2 Engine-specifc encoder allocation") |
| c9ae6e1691cd ("drm/amd/display: Acquire DSC HW resource only if required by stream") |
| 254eb07cb090 ("drm/amd/display: Optimize bandwidth validation by adding early return") |
| ede37e4ce495 ("drm/amd/display: fix can not turn on two displays due to DSC_RESOURCE failed.") |
| 0ba37b20ef1c ("drm/amd/display: fix dsc validation") |
| 00999d991fde ("drm/amd/display: clean up validation failure log spam") |
| 97bda0322b8a ("drm/amd/display: Add DSC support for Navi (v2)") |
| 476e955dd679 ("drm/amd/display: Hook DCN2 into amdgpu_dm and expose as config (v2)") |
| e249428256e2 ("drm/amd/display: updates for dcn20_update_bandwidth") |
| cb0b554abeac ("drm/amd/display: add fast_validate parameter to dcn20_validate_bandwidth") |
| 6fbefb84a98e ("drm/amd/display: Add DC core changes for DCN2") |
| 7ed4e6352c16 ("drm/amd/display: Add DCN2 HW Sequencer and Resource") |
| 345429a67c48 ("drm/amd/display: Add DCN2 DWB") |
| 2d78b3a177fe ("drm/amd/display: Add DCN2 OPTC") |
| ca4d9b3a5a3b ("drm/amd/display: Add DCN2 DIO") |
| 728c06986a4f ("drm/amd/display: Add DCN2 changes to DML") |
| 48321c3dde79 ("drm/amd/display: Read soc_bounding_box from gpu_info (v2)") |
| 35c2e91059cb ("drm/amdgpu: parse the new members added by gpu_info ucode v1_1") |
| 109c80ddb40f ("drm/amdgpu: add gpu_info_firmware v1_1 structure for navi10") |
| c5c07cb5435e ("drm/amd/display: Refactor DIO stream encoder") |
| 961ea20155d7 ("drm/amd/display: Fix type of pp_smu_wm_set_range struct") |
| e63e2491ad92 ("drm/amd/display: Ensure DRR triggers in BP") |
| 313a9a21ff46 ("drm/amd/display: Add GSL source select registers") |
| dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific") |
| 78cc70b1e47d ("drm/amd/display: Engine-specific encoder allocation") |
| 6476a7c8f031 ("drm/amd/display: Program VTG params after programming Global Sync") |
| 24c18794946a ("drm/amd/display: add null checks and set update flags") |
| 97df424fe7a7 ("drm/amd/display: Drop DCN1_01 guards") |
| d7316ddc610f ("drm/amd/display: Add ASICREV_IS_PICASSO") |
| 88ccdf1d59df ("drm/amd/display: Expose send immediate sdp message interface") |
| b2293ac23776 ("drm/amd/display: move back vbios cmd table for set dprefclk") |
| e7e10c464a48 ("drm/amd/display: stop external access to internal optc sync params") |
| db819940b0ef ("drm/amd/display: move signal type out of otg dlg params") |
| 21e471f0850d ("drm/amd/display: Set dispclk and dprefclock directly") |
| 09aef2c48e79 ("drm/amd/display: Compensate for pre-DCE12 BTR-VRR hw limitations. (v3)") |
| a0867053408e ("drm/amd/display: remove deprecated pplib interface") |
| 27eaa4927dc3 ("drm/amd/display: Add power down display on boot flag") |
| f55be0be5b72 ("drm/amd/display: Add profiling tools for bandwidth validation") |
| afcd526b1ba9 ("drm/amd/display: Add fast_validate parameter") |
| c7e557ab46a7 ("drm/amd/display: Clean up locking in dcn*_apply_ctx_for_surface()") |
| c85fc65e2241 ("drm/amd/display: init dc_config before rest of DC init") |
| b4423fd9cf3e ("drm/amd/display: return correct dc_status for dcn10_validate_global") |
