| e11ea2a02b93 ("riscv: optimize send_ipi_single") |
| 7e0e50895fdf ("riscv: refactor the IPI code") |
| 58de77545e53 ("riscv: move flush_icache_{all,mm} to cacheflush.c") |
| a3182c91ef4e ("RISC-V: Access CSRs using CSR numbers") |
| df16c40cbfb4 ("riscv: clear all pending interrupts when booting") |
| 37a107ff6dcd ("riscv: don't stop itself in smp_send_stop") |
| 8b20d2db0a6d ("RISC-V: Show IPI stats") |
| f99fb607fb2b ("RISC-V: Use Linux logical CPU number instead of hartid") |
| 6825c7a80f18 ("RISC-V: Add logical CPU indexing for RISC-V") |
| a37d56fc4011 ("RISC-V: Use WRITE_ONCE instead of direct access") |
| 177fae451588 ("RISC-V: Rename im_okay_therefore_i_am to found_boot_cpu") |
| b2f8cfa7ac34 ("RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid") |
| 19ccf29bb18f ("RISC-V: Filter ISA and MMU values in cpuinfo") |
| 1ed4237ab616 ("RISC-V: No need to pass scause as arg to do_IRQ()") |
