| 8b91fd8bb192 ("drm/amd/display: work around fp code being emitted outside of DC_FP_START/END") |
| 7a8a3430be15 ("amdgpu: Wrap FPU dependent functions in dc20") |
| d9e32672a128 ("drm/amd/display: cleanup of construct and destruct funcs") |
| d9a07577b8a3 ("drm/amd/display: add oem i2c implemenation in dc") |
| 5622b2d68d0a ("drm/amd/display: Create debug option to disable v.active clock change policy.") |
| 1cad8ff7ecc6 ("drm/amd/display: Renoir chroma viewport WA") |
| 47f365645a3b ("drm/amd/display: Fix assert observed when performing dummy p-state check") |
| 6fcca317cb70 ("drm/amd/display: Apply vactive dram clock change workaround to dcn2 DMLv2") |
| 4294f722196d ("drm/amd/display: add 50us buffer as WA for pstate switch in active") |
| 57133a28bcaf ("drm/amd/display: fix code to control 48mhz refclk") |
| 9ae1b27f31d0 ("drm/amd/display: fix hotplug during display off") |
| 7f7652ee8c8c ("drm/amd/display: enable single dp seamless boot") |
| 6f4e6361c3ff ("drm/amd/display: Add Renoir resource (v2)") |
| 4edb6fc91878 ("drm/amd/display: Add Renoir clock manager") |
| 6f451b60e044 ("drm/amd/display: Add Renoir Hubbub (v2)") |
| eced51f9babb ("drm/amd/display: Add hubp block for Renoir (v2)") |
| 1e768c5b0f44 ("drm/amd/display: Add Renoir irq_services (v2)") |
| 675a9e38b39c ("drm/amd/display: Load NV12 SOC BB from firmware") |
| e7f2c80cbaab ("drm/amd/display: check hpd before retry verify link cap") |
| b5b1f4554904 ("drm/amd/display: Enable type C hotplug") |
| 1071a0ecf4a6 ("drm/amd/display: Update DML parameters") |
| b9e8d95a7bc2 ("drm/amd/display: clean up DML for DCN2x") |
| 5ec43eda8550 ("drm/amd/display: enabling seamless boot sequence for dcn2") |
| 8a31820b1218 ("drm/amd/display: Make init_hw and init_pipes generic for seamless boot") |
| 91db9311945f ("drm/amd/display: refactor gpio to allocate hw_container in constructor") |
| 37495fbdf12d ("drm/amd/display: Add work-around option to skip DCN20 clock updates") |
| 9adc8050bf3c ("drm/amd/display: make firmware info only load once during dc_bios create") |
| ac42fd639550 ("drm/amd/display: reset hdmi tmds rate and data scramble on pipe reset") |
| f16d523f9d83 ("drm/amd/display: Support uclk switching for DCN2") |
| fb6959ae5017 ("drm/amd/display: Embed DCN2 SOC bounding box") |
| d3b9f39d8417 ("drm/amdgpu/display: fix the build without CONFIG_DRM_AMD_DC_DSC_SUPPORT") |
| 057fc695e934 ("drm/amd/display: support "dummy pstate"") |
| dcbb45b6eeed ("drm/amd/display: do not read link setting if edp not connected") |
| f591344e89dc ("drm/amd/display: Clean up dynamic metadata logic") |
| 39bca3599aab ("drm/amd/display: add a option to force the clock at every mode change.") |
| 925f566cb7ae ("drm/amd/display: add set and get clock for testing purposes") |
| c2cd9d04ecf0 ("drm/amd/display: Hook up calls to do stereo mux and dig programming to stereo control interface") |
| 290129c25617 ("drm/amd/display: Add CM_BYPASS via debug option") |
| 70f1476a7eed ("drm/amd/display: Add debug option to disable timing sync") |
| c43f89f81cc0 ("drm/amd/display: put back front end initialization sequence") |
| d40605b6d088 ("drm/amd/display: Implement generic MUX registers (v2)") |
| 75c35000235f ("drm/amd/display: Power-gate all DSCs at driver init time") |
| 24f1d1cee2bc ("drm/amd/display: Check for valid stream_encode") |
| 6de202373bf6 ("drm/amd/display: move bw calc code into helpers") |
| e0a6440a2961 ("drm/amd/display: Add ability to set preferred link training parameters.") |
| 93c25fbdc30a ("drm/amd/display: initialize p_state to proper value") |
| 41a5a2a8531f ("drm/amd/display: init res_pool dccg_ref, dchub_ref with xtalin_freq") |
| 02316e963a5a ("drm/amd/display: Force uclk to max for every state") |
| 709527c77a89 ("drm/amd/display: update infoframe after dig fe is turned on (v2)") |
| 170a2398d2d8 ("drm/amd/display: make clk_mgr call enable_pme_wa") |
