| bf7f5ac3167a ("drm/amd/display: map TRANSMITTER_UNIPHY_x to LINK_REGS_x") |
| 91c665bdc1d5 ("drm/amd/display: create dcn21_link_encoder files") |
| c0fb59a4c3f5 ("drm/amd/display: Add renoir hw_seq") |
| 8276dd871fd4 ("drm/amd/display: update register field access mechanism") |
| 6f4e6361c3ff ("drm/amd/display: Add Renoir resource (v2)") |
| 6f451b60e044 ("drm/amd/display: Add Renoir Hubbub (v2)") |
| eced51f9babb ("drm/amd/display: Add hubp block for Renoir (v2)") |
| ab6183122786 ("drm/amd/display: Add Renoir hw_seq register list") |
| 8a31820b1218 ("drm/amd/display: Make init_hw and init_pipes generic for seamless boot") |
| 9adc8050bf3c ("drm/amd/display: make firmware info only load once during dc_bios create") |
| d3b9f39d8417 ("drm/amdgpu/display: fix the build without CONFIG_DRM_AMD_DC_DSC_SUPPORT") |
| f591344e89dc ("drm/amd/display: Clean up dynamic metadata logic") |
| 925f566cb7ae ("drm/amd/display: add set and get clock for testing purposes") |
| c43f89f81cc0 ("drm/amd/display: put back front end initialization sequence") |
| 75c35000235f ("drm/amd/display: Power-gate all DSCs at driver init time") |
| 24f1d1cee2bc ("drm/amd/display: Check for valid stream_encode") |
| 41a5a2a8531f ("drm/amd/display: init res_pool dccg_ref, dchub_ref with xtalin_freq") |
| 709527c77a89 ("drm/amd/display: update infoframe after dig fe is turned on (v2)") |
| 170a2398d2d8 ("drm/amd/display: make clk_mgr call enable_pme_wa") |
| 7a5ab155d34a ("drm/amd/display: expose dentist_get_did_from_divider") |
| 1a7d296d162e ("drm/amd/display: Add Underflow Asserts to dc") |
| 043f5bb630c1 ("drm/amd/display: Use macro for invalid OPP ID") |
| 040a4d63bde4 ("drm/amd/display: DCHUB requestors numbers for Navi.") |
| 4850ce697f98 ("drm/amd/display: Add hubp_init entry to hubp vtable") |
| 4e0cbbbfbc37 ("drm/amd/display: Clean up locking in dcn*_apply_ctx_for_surface()") |
| 45021f8ea536 ("drm/amd/display: do not power on eDP power rail early") |
| 98b5b65eb8b7 ("drm/amd/display: disable PSR/ABM before destroy DMCU struct") |
| 284358f2acc1 ("drm/amd/display/dc: fix azalia workaround sw implementation bug") |
| 97bda0322b8a ("drm/amd/display: Add DSC support for Navi (v2)") |
| 476e955dd679 ("drm/amd/display: Hook DCN2 into amdgpu_dm and expose as config (v2)") |
| 6fbefb84a98e ("drm/amd/display: Add DC core changes for DCN2") |
| 7ed4e6352c16 ("drm/amd/display: Add DCN2 HW Sequencer and Resource") |
| 345429a67c48 ("drm/amd/display: Add DCN2 DWB") |
| bbeb64d0eb78 ("drm/amd/display: Add DCN2 HUBP and HUBBUB") |
| 2d78b3a177fe ("drm/amd/display: Add DCN2 OPTC") |
| fcee01b9f82d ("drm/amd/display: Add DCN2 clk mgr") |
| ca4d9b3a5a3b ("drm/amd/display: Add DCN2 DIO") |
| 38e7128960a6 ("drm/amd/display: add AUX and I2C for DCN2") |
| 48321c3dde79 ("drm/amd/display: Read soc_bounding_box from gpu_info (v2)") |
| 35c2e91059cb ("drm/amdgpu: parse the new members added by gpu_info ucode v1_1") |
| 109c80ddb40f ("drm/amdgpu: add gpu_info_firmware v1_1 structure for navi10") |
| c5c07cb5435e ("drm/amd/display: Refactor DIO stream encoder") |
| baa1fd7f32f2 ("drm/amd/display: Refactor clk_mgr functions") |
| 961ea20155d7 ("drm/amd/display: Fix type of pp_smu_wm_set_range struct") |
| 9b93eb475aa9 ("drm/amd/display: move clk_mgr files to right place") |
| e63e2491ad92 ("drm/amd/display: Ensure DRR triggers in BP") |
| 313a9a21ff46 ("drm/amd/display: Add GSL source select registers") |
| dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific") |
| 78cc70b1e47d ("drm/amd/display: Engine-specific encoder allocation") |
| 6476a7c8f031 ("drm/amd/display: Program VTG params after programming Global Sync") |
