| d8dfc3bd461d ("drm/amdgpu: fix warning on 32 bit") |
| dc8ae677c2a0 ("drm/amdgpu/VCN: implement indirect DPG SRAM mode") |
| bf4865b587c0 ("drm/amdgpu/VCN2.0: add DPG mode start and stop (v2)") |
| 19c663fc7799 ("drm/amdgpu/VCN2.0: add direct SRAM read and write") |
| b3ef5ce0379b ("drm/amdgpu/VCN2.0 remove unused Macro and declaration") |
| 0b8794e252fc ("drm/amdgpu/vcn2: don't access register when power gated") |
| c113ba157f41 ("drm/amdgpu/vcn2: notify SMU power up/down VCN") |
| 1b61de45dfaf ("drm/amdgpu: add initial VCN2.0 support (v2)") |
| 05eee12dd60e ("drm/amdgpu: move the VCN DPG mode read and write to VCN") |
| 6b1ff3ddc66d ("drm/amdgpu: add basic func for RLC program reg") |
| 03d6e3aac816 ("drm/amdgpu:Add DPG mode read/write macro") |
| d58c5d9a4205 ("drm/amdgpu: Add VCN static PG support on RV") |
| c9dc5abb661b ("drm/amdgpu: Add static CG control for VCN on RV") |
| 0ad6f0d387da ("drm/amd/amdgpu: Port VCN over to new SOC15 macros") |
| d2a33871b54c ("drm/amdgpu: enable sw clock gating for vcn") |
| fb4d56fa3724 ("drm/amdgpu/vcn: add sw clock gating") |
| 62a9f37e4cea ("drm/amdgpu: add vcn firmware header offset") |
| 8ace845ff0e8 ("drm/amdgpu: add vcn enc ring type and functions") |
| 101c6fee53f6 ("drm/amdgpu: add vcn enc rings") |
| 81439659f4b8 ("drm/amdgpu: implement new vcn cache window programming") |
| 7741cced67ae ("drm/amdgpu: expose vcn RB command") |
| 95aa13f6b196 ("drm/amdgpu: move amdgpu_vcn structure to vcn header") |
| a319f444bb86 ("drm/amdgpu: add vcn irq functions") |
| cca69fe8ff98 ("drm/amdgpu: add vcn decode ring type and functions") |
| a4bf608be5df ("drm/amdgpu: add vcn decode ring support") |
| 88b5af70e29e ("drm/amdgpu: add vcn ip block functions (v2)") |
| 95d0906f8506 ("drm/amdgpu: add initial vcn support and decode tests") |
| 70170d146d0f ("drm/amdgpu: add clinetid definition for vega10") |
| 8e3153ba3f62 ("drm/amdgpu: add common soc15 headers") |
| 50c3e2329968 ("drm/amdgpu: add uvd enc ring type and functions") |
| 5e5681788bef ("drm/amdgpu: move amdgpu_vce structure to vce header") |
| 4df654d293c6 ("drm/amdgpu: move amdgpu_uvd structure to uvd header") |
| d766e6a39338 ("drm/amdgpu: switch ih handling to two levels (v3)") |
| 254cd2e08dd0 ("drm/amdgpu: read hw register to check pg status.") |
| 6fc11b0ed354 ("drm/amdgpu: refine vce3.0 code and related powerplay pg code.") |
| 3a78696658a0 ("drm/amdgpu: power down/up uvd4 when smu disabled.") |
| ab71ac56f6d8 ("drm/amdgpu/virt: implement VI virt operation interfaces") |
| 1e9f1392795e ("drm/amdgpu/virt: add high level interfaces for virt") |
| bc992ba5a3c1 ("drm/amdgpu/virt: use kiq to access registers (v2)") |
| 880e87e38098 ("drm/amdgpu/gfx8: implement emit_rreg/wreg function") |
| 4e4bbe7343a6 ("drm/amdgpu:add new file for SRIOV") |
| bd7de27d81a7 ("drm/amdgpu:new field members for SRIOV") |
| c79b55618a9c ("drm/amdgpu: add get clockgating_state method for vce v3") |
| c8781f56c859 ("drm/amdgpu: add get clockgating_state method for uvd v5&v6") |
| 5a5099cbf4d8 ("drm/amdgpu/virt: rename fieldes of virtualization structure") |
| 4e638ae9c1e7 ("drm/amdgpu/gfx8: add support kernel interface queue(KIQ)") |
| 3731d12dce83 ("drm/amd/powerplay: fix vce cg logic error on CZ/St.") |
| 84f3f05b4432 ("drm/amdgpu: Don't touch GFX hw during HW fini") |
| aa4747c00a2d ("drm/amdgpu: refine uvd_4.2 clock gate sequence.") |
| 2068751d0941 ("drm/amdgpu: Add a ring type KIQ definition") |
