| 0dea3f35996f ("clk: meson: gxbb: migrate to the new parent description method") |
| c0e6f5bf7676 ("clk: meson: gxbb: claim clock controller input clock from DT") |
| 8913e8a73d03 ("clk: meson: Mark some things static") |
| a8080f247bcd ("clk: meson-gxbb: Add video clocks") |
| 0058502fb93a ("clk: meson-gxbb: Fix HDMI PLL for GXL SoCs") |
| 72dbb8c94d0d ("clk: meson: Add vid_pll divider driver") |
| 87173557d2f6 ("clk: meson: clk-pll: remove od parameters") |
| 2303a9ca693e ("clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary") |
| e40c7e3cda07 ("clk: meson: clk-pll: add enable bit") |
| 7df533a7e3d2 ("clk: meson: add gen_clk") |
| cddcb20b2bb3 ("clk: meson-axg: add clocks required by pcie driver") |
| 85ddc1a32cac ("clk: meson: remove unused clk-audio-divider driver") |
| 9799d5ae003c ("clk: meson: stop rate propagation for audio clocks") |
| 3054a55c5dd2 ("clk: meson: add axg audio sclk divider driver") |
| e8dd9207763e ("clk: meson: add triple phase clock driver") |
| 47f21315a6e4 ("clk: meson: add clk-phase clock driver") |
| 60e267f3fd73 ("clk: meson: remove obsolete register access") |
| 7813c14c9475 ("clk: meson: audio-divider is one based") |
| bae1106c37c6 ("clk: meson: mpll: add round closest support") |
| 22f65a389f61 ("clk: meson: use SPDX license identifiers consistently") |
| 88e2da81241e ("clk: meson: aoclk: refactor common code into dedicated file") |
| bdfa6394c229 ("clk: meson: migrate to devm_of_clk_add_hw_provider API") |
| a565242eb9fc ("clk: meson: gxbb: add the video decoder clocks") |
| b8c1ddadc815 ("clk: meson: meson8b: add support for the NAND clocks") |
| 5d1c04dde0eb ("clk: meson: Drop unused local variable and add static") |
| 5b13ef64eebd ("clk: meson: clean-up clk81 clocks") |
| 05f814402d61 ("clk: meson: add fdiv clock gates") |
| 513b67ac39b0 ("clk: meson: add mpll pre-divider") |
| 093c3fac4619 ("clk: meson: axg: add hifi pll clock") |
| 0a1be867b92a ("clk: meson: add ROUND_CLOSEST to the pll driver") |
| c77de0e5c95a ("clk: meson: add gp0 frac parameter for axg and gxl") |
| 8289aafa4f36 ("clk: meson: improve pll driver results with frac") |
| c178b003bfcf ("clk: meson: remove special gp0 lock loop") |
| 117863e84247 ("clk: meson: poke pll CNTL last") |
| 2eab2d7cab28 ("clk: meson: add fractional part of meson8b fixed_pll") |
| 4162dd5b3a17 ("clk: meson: use hhi syscon if available") |
| 03a6519e9cd4 ("clk: meson: remove obsolete cpu_clk") |
| 251b6fd38bcb ("clk: meson: rework meson8b cpu clock") |
| d610b54f7700 ("clk: meson: split divider and gate part of mpll") |
| 722825dcd54b ("clk: meson: migrate plls clocks to clk_regmap") |
| 88a4e1283681 ("clk: meson: migrate the audio divider clock to clk_regmap") |
| c763e61ae8cb ("clk: meson: migrate mplls clocks to clk_regmap") |
| 2513a28c108b ("clk: meson: migrate muxes to clk_regmap") |
| f06ddd2852b3 ("clk: meson: migrate dividers to clk_regmap") |
| 7f9768a54051 ("clk: meson: migrate gates to clk_regmap") |
| 161f6e5baabd ("clk: meson: add regmap to the clock controllers") |
| 81c7fcac9b5f ("clk: meson: switch gxbb ao_clk to clk_regmap") |
| ea11dda9e091 ("clk: meson: add regmap clocks") |
| 7b174c5ebe46 ("clk: meson: remove obsolete comments") |
| 14bd7b9c8d3f ("clk: meson: only one loop index is necessary in probe") |
