| 5f8d084939d0 ("drm/amd/display: add CHG_DONE mash/sh defines for dentist") |
| 3cdecd4513d5 ("drm/amd/display: rename dce_disp_clk to dccg") |
| 472800a0a0c8 ("drm/amd/display: clean up dccg divider calc and dcn constructor") |
| 12c3130dd6f3 ("drm/amd/display: move dcn1 dispclk programming to dccg") |
| d578839ca014 ("drm/amd/display: get rid of cur_clks from dcn_bw_output") |
| e2e0a1dcd322 ("drm/amd/display: move clock programming from set_bandwidth to dccg") |
| 6ca11246180a ("drm/amd/display: rename display clock block to dccg") |
| fab55d61b9f0 ("drm/amd/display: redesign dce/dcn clock voltage update request") |
| 765b26836430 ("drm/amd/display: replace clocks_value struct with dc_clocks") |
| 5099114ba3b2 ("drm/amdgpu/display: drop DRM_AMD_DC_FBC kconfig option") |
| 1a05873f21d6 ("drm/amd/display: Refactor audio programming") |
| eb0e515464e4 ("drm/amd/display: get rid of 32.32 unsigned fixed point") |
| 87ac8fb08bc7 ("drm/amd/display: disable FBC on underlay pipe") |
| 55a01d4023ce ("drm/amd/display: Add user_regamma to color module") |
| a47654633596 ("drm/amd/display: add calculated clock logging to DTN") |
| 0a93dc7f595f ("drm/amd/display: add rq/dlg/ttu to dtn log") |
| 2fa417324abd ("drm/amd/display: Remove PRE_VEGA flag") |
| 5c6161162a55 ("drm/amd/display: Do not use os types") |
| 0c41891c81c0 ("drm/amd/display: Refactor stream encoder for HW review") |
| 3032deb52a6b ("drm/amd/display: Correct print types in DC_LOGS") |
| 6da2b9332c57 ("amdgpu/dm: Default PRE_VEGA ASIC support to 'y'") |
| 17ac50368f83 ("drm/amd/display: clean up dcn pplib notification call") |
| 45bb8dd696ea ("drm/amd/display: Set disp clk in a safe way to avoid over high dpp clk. (v2)") |
| a4056c2a6344 ("drm/amd/display: use HW hdr mult for brightness boost") |
| 8e437c799158 ("drm/amd/display: Modified set bandwidth sequence.") |
| 90e3103e1966 ("drm/amd/display: Fix takover from VGA mode") |
| 623a7e96cd73 ("drm/amd/display: Remove 300Mhz minimum disp clk limit.") |
| 28d4175413ef ("drm/amd/display: fix dcn1 dppclk when min dispclk patch applies") |
| 1296423bf23c ("drm/amd/display: define DC_LOGGER for logger") |
| 2f3fd67a8af2 ("drm/amd/display: Use MACROS instead of dm_logger") |
| 44c6f2e59ee8 ("drm/amd/display: Handle HDR use cases.") |
| 15cf3974eb06 ("drm/amd/display: add diags clock programming") |
| f553e6810259 ("drm/amd/display: add per pipe dppclk") |
| ea7ea2a8cac1 ("drm/amd/display: fix missing az disable in reset backend") |
| 3d53f424796b ("drm/amd/display: update cur_clock correctly within set bandwidth") |
| 086247a4b2fb ("drm/amd/display: Use 4096 lut entries") |
| 792474b73627 ("drm/amd/display: De PQ implementation") |
| fdf0c1c2f75e ("drm/amd/display: Add logging for aux DPCD access") |
| 3e332d3a5a64 ("drm/amd/display: Make FBC work without fbdev emulation") |
| 236d0e4f6f1e ("drm/amd/display: Refactor max color lut entries into a macro.") |
| e277adc5a06c ("drm/amd/display: Hookup color management functions") |
| 303afd2dbf1b ("drm/amd/display: Implement color management") |
| ec7e6bb81491 ("drm/amd/display: Add color module's gamma helpers to Linux build") |
| 4cac1e6d2ffa ("drm/amd/display: Keep eDP stream enabled during boot.") |
| 91d4a1290034 ("drm/amd/display: boot up/S4 fix mainlink off before BL.") |
| 25b304471846 ("drm/amd/display: enable #PME code path for RV.") |
| 8f8372c7d177 ("drm/amd/display: Optimize regamma calculations") |
| c5fc7f59a71a ("drm/amd/display: resume from S3 bypass power down HW block.") |
| 5180d4a4766d ("drm/amd/display: add eDP 1.2+ polling for T7") |
| a6e59fa8061b ("drm/amd/display: WBSCL filter init calculation fixes") |
