| a9b84b449277 ("drm/i915/icl: create function to identify combophy port") |
| dccc7228b5de ("drm/i915/icl: Add DDI HDMI level selection for ICL") |
| 51c83cfaf963 ("drm/i915/icl: Get DDI clock for ICL based on PLLs.") |
| ac213c1b45f7 ("drm/i915/icl: introduce tc_port") |
| c27e917e2bda ("drm/i915/icl: add basic support for the ICL clocks") |
| 36cf89f53b0c ("drm/i915/icl: Fix the DP Max Voltage for ICL") |
| fb5c8e9d4350 ("drm/i915/icl: Implement voltage swing programming sequence for Combo PHY DDI") |
| 2320175feb74 ("drm/i915: Implement HDCP for HDMI") |
| 09a28bd9e802 ("drm/i915: Move display related definitions to dedicated header") |
| b74eeeb6b1ab ("drm/i915: Move some utility functions to i915_util.h") |
| 8edcda1266f9 ("drm/i915: Protect DDI port to DPLL map from theoretical race.") |
| b68763741aa2 ("drm/i915: Restore GT performance in headless mode with DMC loaded") |
| dd57602efbce ("drm/i915: Switch fbc over to for_each_new_intel_plane_in_state()") |
| ed15030d7ab0 ("drm/i915: s/enum plane/enum i9xx_plane_id/") |
| b1e01595a66d ("drm/i915: Redo plane sanitation during readout") |
| 51f5a0963984 ("drm/i915: Add .get_hw_state() method for planes") |
| d02ace874937 ("drm/i915: Drop the redundant hdmi prefix/suffix from a lot of variables") |
| 21b39d2a3adb ("drm/i915: Unify error handling for missing DDI buf trans tables") |
| 043eaf3685c8 ("drm/i915: Kill off the BXT buf_trans default_index") |
| f3cf4ba45e13 ("drm/i915: Pass encoder type to cnl_ddi_vswing_sequence() explicitly") |
| 7d4f37b5db57 ("drm/i915: Integrate BXT into intel_ddi_dp_voltage_max()") |
| 7ea79333a728 ("drm/i915: Pass the level to intel_prepare_hdmi_ddi_buffers()") |
| 081dfcfafcbb ("drm/i915: Pass the encoder type explicitly to skl_set_iboost()") |
| 975786ee0e25 ("drm/i915: Extract intel_ddi_get_buf_trans_hdmi()") |
| d8fe2c7f3365 ("drm/i915: Relocate intel_ddi_get_buf_trans_*() functions") |
| 31d1d3c8862e ("drm/i915: adjust get_crtc_fence_y_offset() to use base.y instead of crtc.y") |
| 779d4d8f083e ("drm/i915: Unify skylake plane disable") |
| 9a8cc576002a ("drm/i915: Unify skylake plane update") |
| e288881b08dc ("drm/i915: dspaddr_offset doesn't need to be more than local variable") |
| bf0a5d4b223d ("drm/i915: move adjusted_x/y from crtc to cache.") |
| 1210d3889077 ("drm/i915: Use bdw_ddi_translations_fdi for Broadwell") |
| 45e0327e28e5 ("drm/i915: Plumb crtc_state etc. directly to intel_ddi_pre_enable_{dp,hdmi}()") |
| 680b71c201fc ("drm/i915: Remove useless eDP check from intel_ddi_pre_enable_dp()") |
| 6b8506d575e3 ("drm/i915: Extract intel_ddi_clk_disable()") |
| de330815677d ("drm/i915: Reuse normal state readout for LVDS/DVO fixed mode") |
| 2de3813880bf ("drm/i915: add the BXT and CNL DPLL registers to pipe_config_compare") |
| d0d37254680f ("drm/i915: Use intel_get_pipe_timings() and intel_mode_from_pipe_config() in intel_crtc_mode_get()") |
| e30a154b5262 ("drm/i915: Read timings from the correct transcoder in intel_crtc_mode_get()") |
| 7c26240e8a19 ("drm/i915: Try harder to finish the idle-worker") |
| 364a3fe18235 ("drm/i915: push DDI and DSI underrun reporting on enable to encoder") |
| 3daa3cee6ebc ("drm/i915: push DDI CRT underrun reporting on disable to encoder") |
| 51c4fa6903f9 ("drm/i915: push DDI CRT underrun reporting on enable to encoder") |
| 5ea2355a100a ("drm/i915/mst: Use MST sideband message transactions for dpms control") |
| ed69cd40685c ("drm/i915/glk, cnl: Implement WaDisableScalarClockGating") |
| ac3ad6c66998 ("drm/i915: Shrink bxt_ddi_buf_trans") |
| 7b510451c896 ("drm/i915: Eliminate obj->state usage in g4x/vlv/chv wm computation") |
| d3a8fb3223a7 ("drm/i915: Pass the crtc state explicitly to intel_pipe_update_start/end()") |
| d305e0614601 ("drm/i915: Track minimum acceptable cdclk instead of "minimum dotclock"") |
| 5fcf34b1c58e ("drm/i915/cnl: Fix DP max voltage") |
| bf5035564579 ("drm/i915/cnl: Fix DDI hdmi level selection.") |
