| bb82139b4bbf ("drm/i915/icl: compute the combo PHY (DPLL) DP registers") |
| febafb93181e ("drm/i915/icl: compute the combo PHY (DPLL) HDMI registers") |
| c27e917e2bda ("drm/i915/icl: add basic support for the ICL clocks") |
| 2320175feb74 ("drm/i915: Implement HDCP for HDMI") |
| 8edcda1266f9 ("drm/i915: Protect DDI port to DPLL map from theoretical race.") |
| 063c886197f6 ("drm/i915/cnl: Fix wrpll math for higher freqs.") |
| 5eca81de8892 ("drm/i915/cnl: Fix, simplify and unify wrpll variable sizes.") |
| ecc2069a025e ("drm/i915/cnl: Remove useless conversion.") |
| 6b8506d575e3 ("drm/i915: Extract intel_ddi_clk_disable()") |
| 2de3813880bf ("drm/i915: add the BXT and CNL DPLL registers to pipe_config_compare") |
| 3daa3cee6ebc ("drm/i915: push DDI CRT underrun reporting on disable to encoder") |
| 51c4fa6903f9 ("drm/i915: push DDI CRT underrun reporting on enable to encoder") |
| ed69cd40685c ("drm/i915/glk, cnl: Implement WaDisableScalarClockGating") |
