| f78d5da6e7bd ("drm/i915/tgl: Add Wa_1409825376 to tgl") |
| 5d86923060fc ("drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating") |
| 13e53c5c5337 ("drm/i915/tgl: Introduce initial Tiger Lake workarounds") |
| ebd2de47a19f ("drm/i915: Support whitelist workarounds on all engines") |
| fde938867b92 ("drm/i915/selftests: Verify context workarounds") |
| 11334c6aad95 ("drm/i915: Split engine setup/init into two phases") |
| fa9f668141f4 ("drm/i915: Export intel_context_instance()") |
| 251d46b0875c ("drm/i915/gvt: Pin the per-engine GVT shadow contexts") |
| b226c3491b28 ("Merge drm/drm-next into drm-intel-next-queued") |
