| 1cfcdbf3be31 ("drm/i915: WARN if HDCP signalling is enabled upon disable") |
| dc5b8ed56bb3 ("drm/i915: Implement port sync for SKL+") |
| d4d7d9ca57a4 ("drm/i915: Use REG_FIELD_PREP() & co. for TRANS_DDI_FUNC_CTL2") |
| 02d8ea47dbc3 ("drm/i915: Move icl_get_trans_port_sync_config() into the DDI code") |
| 589a4cd6cc43 ("drm/i915: Move TRANS_DDI_FUNC_CTL2 programming where it belongs") |
| 47bdb1caba0b ("drm/i915/ddi: use struct drm_device based logging") |
| 2c1816af090d ("drm/i915/display: Decrease log level") |
| e57291c2d395 ("drm/i915/display/display: Make WARN* drm specific where drm_device ptr is available") |
| e24bcd34c1dd ("drm/i915/dp: Add all tiled and port sync conns to modeset") |
| b50a1aa6e1e9 ("drm/i915/dp: Compute port sync crtc states post compute_config()") |
| 93a0ed6cc164 ("drm/i915: split intel_modeset_driver_remove() to pre/post irq uninstall") |
| 919e4f07392d ("drm/i915/display: Set TRANS_DDI_MODE_SELECT to default value when clearing DDI select") |
| 6dcde04706d8 ("drm/i915: Move linetime wms into the crtc state") |
| 0560b0c6b36c ("drm/i915: Polish WM_LINETIME register stuff") |
| dc008bf0aa09 ("drm/i915/display: use intel_de_*() functions for register access") |
| f7960e7f8f24 ("drm/i915/ddi: use intel_de_*() functions for register access") |
| d1b2828af0cc ("drm/i915: Fix modeset locks in sanitize_watermarks()") |
| cd49f8180681 ("drm/i915/display: conversion to new struct drm_device logging macros.") |
| 691313ea6214 ("drm/i915: Move encoder variable to tighter scope") |
| ee34801cc0e8 ("drm/i915: Prefer to use the pipe to index the ddb entries") |
| d0eed1545fe7 ("drm/i915: Fix post-fastset modeset check for port sync") |
| b7d02c3a124d ("drm/i915: Pass intel_encoder to enc_to_*()") |
| 43a6d19cace6 ("drm/i915: Pass intel_connector to intel_attached_*()") |
| 7829c92b913f ("drm/i915: Fix MST disable sequence") |
| 60c6a14b489b ("drm/i915/display: Force the state compute phase once to enable PSR") |
| 05a8e45136ca ("drm/i915/display: Use external dependency loop for port sync") |
| 953cac3ec55f ("drm/i915: fix an error code in intel_modeset_all_tiles()") |
| 2dfbf9d2873a ("drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine") |
| 5cf15dfca91c ("drm/i915: Add debug message for FB plane[0].offset!=0 error") |
| d156135e6a54 ("drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned") |
| 7361bdb26c2c ("drm/i915: Add support for non-power-of-2 FB plane alignment") |
| a3d9382bd439 ("drm/i915/dp: Disable Port sync mode correctly on teardown") |
| aee40639cdc3 ("drm/i915/dp: Make port sync mode assignments only if all tiles present") |
| a603f5bd1691 ("drm/i915/dp: Make sure all tiled connectors get added to the state with full modeset") |
| 9eae5e27be4a ("drm/i915: prefer 3-letter acronym for ironlake") |
| 95be34841376 ("drm/i915: prefer 3-letter acronym for icelake") |
| f6df4d46bf1e ("drm/i915: prefer 3-letter acronym for skylake") |
| 1e98f88cea0f ("drm/i915: prefer 3-letter acronym for haswell") |
| 1e1a139d62d1 ("drm/i915: Extend WaDisableDARBFClkGating to icl,ehl,tgl") |
| 080d47bfae80 ("drm/i915/mst: Force modeset on MST slaves when master needs a modeset") |
| 5cb5b370c1be ("drm/i915/display: Prepare for fastset external dependencies check") |
| c59053dc58fa ("drm/i915/dp: Fix MST disable sequence") |
| 659f14158f1f ("drm/i915/display: Always enables MST master pipe first") |
| 6671c367a9be ("drm/i915/tgl: Select master transcoder for MST stream") |
| ee36c7c0c837 ("drm/i915/display: Share intel_connector_needs_modeset()") |
| 4941f35b48f7 ("drm/i915: Make sure CCS YUV semiplanar format checks work") |
| 931cd348bb8d ("drm/i915: Skip rotated offset adjustment for unsupported modifiers") |
| 71df86f0fbf5 ("drm/i915/tgl: Make sure FBs have a correct CCS plane stride") |
| b3e57bccd68a ("drm/i915/tgl: Gen-12 render decompression") |
| e7af90945794 ("drm/i915: Add helpers to select correct ccs/aux planes") |
