| 931971280cf8 ("drm/amdgpu: Remove unnecessary variable shadow in gfx_v9_0_rlcg_wreg") |
| 2e0cc4d48b91 ("drm/amdgpu: revise RLCG access path") |
| 460c484f2411 ("drm/amdgpu: Initialize SPM_VMID with 0xf (v2)") |
| 4cd4c5c064bd ("drm/amdgpu: cleanup vega10 SRIOV code path") |
| 7417846725e9 ("drm/amdgpu/gfx10: add gfx v10_1_1 golden settings for navi14") |
| 47b67bd7d426 ("drm/amdgpu/gfx10: add placeholder for navi14 golden settings") |
| 08473888e09b ("drm/amdgpu/gfx10: set SH_MEM_CONFIG.INITIAL_INST_PREFETCH") |
| a644d85a5cd4 ("drm/amdgpu: add gfx v10 implementation (v10)") |
| e0301317acfe ("drm/amdgpu: Hardcode reg access using L1 security") |
| 05eee12dd60e ("drm/amdgpu: move the VCN DPG mode read and write to VCN") |
| 6b1ff3ddc66d ("drm/amdgpu: add basic func for RLC program reg") |
| 98cad2deaf55 ("drm/amdgpu: Skip setting some regs under Vega10 VF") |
| 470b425019e7 ("drm/amdgpu: call psp to program ih cntl in SR-IOV") |
| 78d481126795 ("drm/amdgpu: init vega10 SR-IOV reg access mode") |
| 5326ad54c5ef ("drm/amdgpu: add gfx9 gpr EDC workaround when RAS is enabled") |
| bb5a2bdf36a8 ("drm/amdgpu: support dpm level modification under virtualization v3") |
| 0133690e0d08 ("drm/amdgpu: change Vega IH ring 1 config") |
| 760a1d55344d ("drm/amdgpu: enable ras on gfx9 (v2)") |
| dc8e3a0c8efb ("drm/amd/powerplay: implement is_support_sw_smu function for new smu") |
| dbe6a97024a6 ("drm/amd/powerplay: implement smu update table function") |
| 86ac88030725 ("drm/amd/powerplay: print clock levels for smu11 (v2)") |
| bed3b3a1e19a ("drm/amd/powerplay: implement get_current_clk_freq for smu11") |
| e66adb1eea90 ("drm/amd/powerplay: add function to get power limit for smu11 (v2)") |
| 133438fa4e60 ("drm/amd/powerplay: add function to populate umd state clk.") |
| d6a4aa825a65 ("drm/amd/powerplay: set defalut dpm table for smu") |
| e1c6f86a915f ("drm/amd/powerplay: implement smu_notify_display_change function for smu11") |
| 2f25158d7db8 ("drm/amd/powerplay: implement feature get&set functions") |
| 6b816d731639 ("drm/amd/powerplay: implement smu feature functions") |
| f6a6b9526cf0 ("drm/amd/powerplay: implement smu_run_afll_btc function") |
| 56c53ad6fe6c ("drm/amd/powerplay: implement smu_init_display for smu11") |
| d76c9e241266 ("drm/amd/powerplay: Change the allocate method of dpm context for smu11.") |
| 00bfaec829c3 ("drm/amd/powerplay: expose the function of smu read argument") |
| c58952737623 ("drm/amd/powerplay: add append_powerplay_table function") |
| 78031c2c4dcd ("drm/amd/powerplay: implement smu vega20_message_map for vega20") |
| e88e4f836c61 ("drm/amd/powerplay: add function to set tool table location for smu11 (v2)") |
| 44619596ebd4 ("drm/amd/powerplay: add function to set min dcef deep sleep for smu11 (v2)") |
| 863651b6fadd ("drm/amd/powerplay: add function to write pptable for smu11 (v2)") |
| 29eed6fafdbd ("drm/amd/powerplay: add function to populate smc pptable for smu11") |
| c6eef2d01d05 ("drm/amd/powerplay: add function to check pptable for smu11") |
| 3e333c6ca1f5 ("drm/amd/powerplay: add function to parse pptable for smu11") |
| 74e07f9d3b77 ("drm/amd/powerplay: add vega20 pptable function file") |
| d72e91c5b7b4 ("drm/amd/powerplay: implement notify_memory_pool_location function for smu11") |
| 0b51d9937845 ("drm/amd/powerplay: implement smu_alloc[free]_memory pool function") |
| 08115f87c38d ("drm/amd/powerplay: implement get_clk_info_from_vbios function for smu11 (v2)") |
| 846f1a035b55 ("drm/amd/powerplay: implement get_vbios_bootup_values function for smu11 (v2)") |
| e98499b44413 ("drm/amd/powerplay: add data structure of bootup values") |
| ce6f7fa8a756 ("drm/amd/powerplay: remove header of smu_v11_0_pptable") |
| f96357a991b9 ("drm/amd/powerplay: implement smu_init(fini)_fb_allocations function") |
| 8bf16963df8c ("drm/amd/powerplay: implement smu_init[fini]_power function for smu11") |
| 142dec6266b2 ("drm/amd/powerplay: implement smu dpm context functions for smu11") |
