| cac91e671ad5 ("drm/i915: Fix includes and local vars order") |
| cd1915460861 ("drm/i915: Adjust CDCLK accordingly to our DBuf bw needs") |
| 4f0b4352bd26 ("drm/i915: Extract cdclk requirements checking to separate function") |
| c93b9b2c7929 ("drm/i915: Decouple cdclk calculation from modeset checks") |
| 0cde0e0ff5f5 ("drm/i915: Nuke skl_ddb_get_hw_state()") |
| 3cf43cdc63fb ("drm/i915: Introduce proper dbuf state") |
| 56f48c1d44f6 ("drm/i915: Unify the low level dbuf code") |
| b3f1ff5b5bf1 ("drm/i915: Polish some dbuf debugs") |
| 20f505f22531 ("drm/i915: Restrict qgv points which don't have enough bandwidth.") |
| 7241c57d3140 ("drm/i915: Add TGL+ SAGV support") |
| d8d5afe35e3f ("drm/i915: Make active_pipes check skl specific") |
| 1d0a6c8486aa ("drm/i915: Extract skl SAGV checking") |
| d9162348db12 ("drm/i915: Introduce skl_plane_wm_level accessor.") |
| 9ff79708c54d ("drm/i915: Rename bw_state to new_bw_state") |
| ecab0f3d055d ("drm/i915: Track active_pipes in bw_state") |
| 9728889f42b9 ("drm/i915: Use bw state for per crtc SAGV evaluation") |
| 81b55ef1f47b ("drm/i915: drop a bunch of superfluous inlines") |
| 680e1af713d9 ("drm/i915: Add pre/post plane updates for SAGV") |
| a389c49fac55 ("drm/i915: Prepare to extract gen specific functions from intel_can_enable_sagv") |
| 419190429cd1 ("drm/i915/hdmi: use struct drm_device based logging") |
| 23baedd217ef ("drm/i915: Don't check for wm changes until we've compute the wms fully") |
| a66d7c1e8923 ("drm/i915/display/power: Make WARN* drm specific where drm_priv ptr is available") |
| b04002f4dbee ("drm/i915: Read rawclk_freq earlier") |
| 0f8839f5f323 ("drm/i915: Force state->modeset=true when distrust_bios_wm==true") |
| b18e249bf616 ("drm/i915: Ensure no conflicts with BIOS when updating Dbuf") |
| 067dde902f71 ("drm/i915/hdmi: prefer to_i915() over drm->dev_private to get at i915") |
| 0fde0b1daac9 ("drm/i915/tgl: Update cdclk voltage level settings") |
| 9d5fd37ed7e2 ("drm/i915/ehl: Update port clock voltage level requirements") |
| ff2cd8635e41 ("drm/i915: Correctly map DBUF slices to pipes") |
| 0f0f9aeee334 ("drm/i915: Manipulate DBuf slices properly") |
| 2570b7e3c561 ("drm/i915: Introduce parameterized DBUF_CTL") |
| 85487cf4a167 ("drm/i915: Update dbuf slices only with full modeset") |
| b06cf5953339 ("drm/i915: Move dbuf slice update to proper place") |
| 072fcc306be3 ("drm/i915: Remove skl_ddl_allocation struct") |
| 0c2d55128f33 ("drm/i915: Store active_pipes bitmask in cdclk state") |
| 28a30b45f5e9 ("drm/i915: Convert cdclk to global state") |
| aac978718bb4 ("drm/i915: Introduce intel_calc_active_pipes()") |
| fd1a9bba73fa ("drm/i915: Convert bandwidth state to global state") |
| 0ef1905ecf2e ("drm/i915: Introduce better global state handling") |
| 5f34299384cb ("drm/i915: Move intel_atomic_state_free() into intel_atomic.c") |
| 4c029c499fb4 ("drm/i915: swap() the entire cdclk state") |
| 1965de63a93a ("drm/i915: Extract intel_cdclk_state") |
| 5604e9ceaed5 ("drm/i915: Simplify intel_set_cdclk_{pre,post}_plane_update() calling convention") |
| 0bb94e03834e ("drm/i915: s/cdclk_state/cdclk_config/") |
| 65c88a866d70 ("drm/i915: s/need_cd2x_updare/can_cd2x_update/") |
| b4db3a8c689b ("drm/i915: Collect more cdclk state under the same roof") |
| 54f09d2342b0 ("drm/i915: Move more cdclk state handling into the cdclk code") |
| f119a5e2a4ca ("drm/i915: Nuke skl wm.dirty_pipes bitmask") |
| 6dcde04706d8 ("drm/i915: Move linetime wms into the crtc state") |
| 0560b0c6b36c ("drm/i915: Polish WM_LINETIME register stuff") |
