| e09d40bdbac0 ("drm/amdgpu: change how we update mmRLC_SPM_MC_CNTL") |
| 460c484f2411 ("drm/amdgpu: Initialize SPM_VMID with 0xf (v2)") |
| a644d85a5cd4 ("drm/amdgpu: add gfx v10 implementation (v10)") |
| 1b3f6bc96883 ("drm/amdgpu: increase the MAX ring number") |
| 88dfc9a3dd47 ("drm/amdgpu: separate amdgpu_rlc into a single file") |
| fdb81fd788a7 ("drm/amdgpu: unify rlc function into structure") |
| 7a3e0bb2a574 ("drm/amdgpu: Load fw between hw_init/resume_phase1 and phase2") |
| 0a4f25205ec3 ("drm/amdgpu: split ip hw_init into 2 phases") |
| c8963ea4ce17 ("drm/amdgpu: Split amdgpu_ucode_init/fini_bo into two functions") |
| 744a522794bd ("drm/amd/pp: Allocate ucode bo in request_smu_load_fw") |
| 07da6aa47f84 ("drm/amdgpu: Don't reallocate ucode bo when suspend") |
| 9b008fb7ede3 ("drm/amdgpu: Remove FW_LOAD_DIRECT type support on VI") |
| 5e161e5442a8 ("drm/amd/pp: Refine smu7/8 request_smu_load_fw callback function") |
| 722ca51d4f50 ("drm/amdgpu: Remove redundant code in gfx_v8_0.c") |
| 5d944aaa3c47 ("drm/amdgpu: Halt rlc/cp in rlc_safe_mode") |
| 19a86c08510f ("drm/amd/pp: Return error immediately if load firmware failed") |
| 36859cd5354b ("drm/amdgpu: Change kiq initialize/reset sequence on gfx8") |
| 6c10b5cc4eaa ("drm/amdgpu: Remove duplicate code in gfx_v8_0.c") |
| 05df1f01b292 ("drm/amdgpu: Set power ungate state when suspend/fini") |
| 6c1fd99bc669 ("drm/amdgpu: Cancel gfx off delay work when driver fini/suspend") |
| 448fe1928ce4 ("drm/amdgpu: move gfx definitions into amdgpu_gfx header") |
| 408acede8732 ("drm/amdgpu: Ctrl gfx off via amdgpu_gfx_off_ctrl") |
| 1e317b99f0c2 ("drm/amdgpu: Put enable gfx off feature to a delay thread") |
| d23ee13fba23 ("drm/amdgpu: Add amdgpu_gfx_off_ctrl function") |
| 4a8c21a1e9b3 ("drm/amdgpu: move bo_list defines to amdgpu_bo_list.h") |
| 52c054caf830 ("drm/amdgpu: add proper error handling to amdgpu_bo_list_get") |
| e7854a038015 ("drm/amdgpu: split ip suspend into 2 phases") |
| 050d9d43a7d3 ("drm/amdgpu: cleanup job header") |
| 964d0fbf6301 ("drm/amdgpu: Allow to create BO lists in CS ioctl v3") |
| d92867122cd9 ("drm/amdgpu/pp/smu7: cache smu firmware toc") |
| 2bce4be03738 ("drm/amdgpu/pp/smu7: drop unused values in smu data structure") |
| 3d75a8b689af ("drm/amdgpu/pp/smu7: use a local variable for toc indexing") |
| 991a6b32ce64 ("drm/amd/powerplay: add vega12 SMU gfxoff support v3") |
| d26031c113ac ("drm/amdgpu: drop mmRLC_PG_CNTL clear v2") |
| 70fef5741c6b ("drm/amd/powerplay: retrieve all clock ranges on startup") |
| 9134c6d7f288 ("drm/amdgpu: Add gfx_off support in smu through pp_set_powergating_by_smu") |
| 85f80cb3af10 ("drm/amd/pp: Add gfx pg support in smu through set_powergating_by_smu") |
| b92c628712ed ("drm/amd/pp: Unify powergate_uvd/vce/mmhub to set_powergating_by_smu") |
| 3eb6e4795de3 ("drm/amd/pp: Rename enable_per_cu_power_gating to powergate_gfx") |
| a8da8ff3332b ("drm/amdgpu: Rename set_mmhub_powergating_by_smu to powergate_mmhub") |
| 9bdc2092b488 ("drm/amdgpu: Add parsing SQ_EDC_INFO to SQ IH v3.") |
| d9e222b460b1 ("drm/amdgpu: Polish SQ IH.") |
| a21daa88d4f0 ("drm/amdgpu: Use correct enum to set powergating state") |
| b1ddf5484727 ("drm/amdgpu: Get real power source to initizlize ac_power") |
| 04ad26bbc41e ("drm/amdgpu: Add plumbing for handling SQ EDC/ECC interrupts v2.") |
| 981658c67a97 ("drm/amdgpu: Add interrupt SQ source struct to amdgpu_gfx struct v2.") |
| 5a2f291343bc ("drm/amdgpu: Added ISR for CP ECC/EDC interrupt v2.") |
| 06b18f61ee78 ("drm/amdgpu: fix CG enabling hang with gfxoff enabled") |
| 3b17c6228562 ("drm/amdgpu/vg20:increase 3 rings for AMDGPU_MAX_RINGS") |
| 8eb77198131b ("drm/amd/powerplay: Add notify PWE function to SMU10") |
