| 09c0533d129c ("soc: sifive: l2 cache: Mark l2_get_priv_group as static") |
| 4a3a37331248 ("riscv: Add support to determine no. of L2 cache way enabled") |
| 13cf4cf03018 ("riscv: move sifive_l2_cache.h to include/soc") |
| 91abaeaaff35 ("EDAC/sifive: Add EDAC platform driver for SiFive SoCs") |
| a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") |
| f6635f873a60 ("riscv: move switch_mm to its own file") |
| a3182c91ef4e ("RISC-V: Access CSRs using CSR numbers") |
| df16c40cbfb4 ("riscv: clear all pending interrupts when booting") |
| 2353ecc6f91f ("bpf, riscv: add BPF JIT for RV64G") |
