| 1d7796bdb63a ("pwm: tegra: Support dynamic clock frequency configuration") | |
| 16216333235a ("treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 1") | |
| 514b044cba66 ("ASoC: tlv320aic32x4: Model PLL in CCF") | |
| c95e3a4b9629 ("ASoC: tlv320aic32x4: Properly Set Processing Blocks") | |
| bf31cbfbe250 ("ASoC: tlv320aic32x4: Break out clock setting into separate function") |