| 2c70c332a1db ("drm/amdgpu: enable hdp CG and LS for dimgrey_cavefish") |
| 135333a0ce4f ("drm/amdgpu: enable mc CG and LS for dimgrey_cavefish") |
| 583e5a5e908b ("drm/amdgpu: enable GFX clock gating for dimgrey_cavefish") |
| cc6161aa7081 ("drm/amdgpu: enable jpeg3.0 PG and CG for dimgrey_cavefish") |
| d5bc1579b0e3 ("drm/amdgpu: enable VCN3.0 PG and CG for dimgrey_cavefish") |
| 467db422cb52 ("drm/amdgpu/vcn: enable VCN DPG mode for dimgrey_cavefish") |
| 550c58e0facd ("drm/amdgpu: add common support for dimgrey_cavefish") |
| 026570e63310 ("drm/amdgpu: add nv common ip block support for van gogh") |
| 543aa2595c23 ("drm/amdgpu/soc15: add support for navy_flounder") |
| dccdbf3f9690 ("drm/amdgpu: initialize IP offset for sienna_cichlid (v2)") |
| 117910ed92b3 ("drm/amdgpu/soc15: add support for sienna_cichlid") |
| 3636169cc0e1 ("drm/amdgpu: Add SRIOV mailbox backend for Navi1x") |
| bebc07628545 ("drm/amdgpu: switch to new amdgpu_nbio structure") |
| f78e007f76bd ("drm/amdgpu: enable clock gating for renoir") |
| f60481a94529 ("drm/amdgpu: add gfx clock gating for Arcturus") |
| b5c73856408b ("drm/amdgpu/discovery: move common discovery code out of navi1*_reg_base_init()") |
| 7e17e58bdde2 ("drm/amdgpu: set nbio/hdp cg for navi12") |
| 03d0a073cf3f ("drm/amdgpu: initialize reg base for navi12") |
| 839f9117e1c2 ("drm/amd/powerplay: guard consistency between CPU copy and local VRAM") |
| 4cd4c5c064bd ("drm/amdgpu: cleanup vega10 SRIOV code path") |
| 4fa1c6a679bb ("drm/amdgpu: add RREG64/WREG64(_PCIE) operations") |
| 64671c0fdc91 ("drm/amdgpu: add perfmon and fica atomics for df") |
| fa739f4b0686 ("drm/amdgpu: add multiple instances support for Arcturus") |
| c01b6a1d3867 ("drm/amdgpu: modify amdgpu_vcn to support multiple instances") |
| 989b6a054997 ("drm/amdgpu: add vcn nbio doorbell range setting for 2nd vcn instance") |
| 530e30fc32d3 ("drm/amdgpu: enable the Doorbell support for VCN2.5") |
| 39a5053fb223 ("drm/amdgpu: add vcn doorbell range function to nbio7.4 (v2)") |
| 800107370810 ("drm/amdgpu/VCN2.5: set JPEG decode ring functions") |
| e87d5a7a23c7 ("drm/amdgpu: add JPEG2.5 HW start and stop") |
| a4767886e5cb ("drm/amdgpu/VCN2.5: set encode ring functions") |
| 185a579700ec ("drm/amdgpu/VCN2.5: set decode ring functions") |
| cbead2bdfcf1 ("drm/amdgpu: add VCN2.5 VCPU start and stop") |
| 28c17d72072b ("drm/amdgpu: add VCN2.5 basic supports") |
| 0e54df05724e ("drm/amdgpu/soc15: add Arcturus common ip blocks") |
| 0fe6a7b49f61 ("drm/amdgpu: support hdp flush for more sdma instances") |
| e78705ec5a7f ("drm/amdgpu: dynamically initialize IP offset for Arcturus") |
| 5e71e011ff84 ("drm/amdgpu/soc15: add support for navi14") |
| c20697674d32 ("drm/amdgpu/discovery: init reg base offset via ip discovery for navi14") |
| a0f6d926f139 ("drm/amdgpu/soc15: initialize reg base for navi14 (v2)") |
| 3e2bb60ab2b1 ("drm/amdgpu: add mode1 (psp) reset for navi asic") |
| 767acabdac81 ("drm/amd/powerplay: add baco smu reset function for smu11") |
| be9a7355e9ee ("drm/amd/powerplay: add interface to get uclk dpm table") |
| a18bf0ca41a9 ("drm/amd/powrplay: add interface for dc to get max clock values") |
| dc8ae677c2a0 ("drm/amdgpu/VCN: implement indirect DPG SRAM mode") |
| a77b9fdf9aca ("drm/amdgpu/VCN: add buffer for indirect SRAM usage") |
| 7282da0b3ac9 ("drm/amdgpu/VCN2.0: add DPG pause mode") |
| bf4865b587c0 ("drm/amdgpu/VCN2.0: add DPG mode start and stop (v2)") |
| 19c663fc7799 ("drm/amdgpu/VCN2.0: add direct SRAM read and write") |
| b3ef5ce0379b ("drm/amdgpu/VCN2.0 remove unused Macro and declaration") |
| 0c83d32c565c ("drm/amd/powerplay: simplified od_settings for each asic") |
