| 2def5ae7d7fb ("drm/i915/dsi: Move vlv/icl_dphy_param_init call out of intel_dsi_vbt_init (v2)") |
| 0e29eb9d9160 ("drm/i915/dsi: Move logging of DSI VBT parameters to a helper function") |
| dee2370ce3d1 ("drm/i915: Adjust DSI fixed mode handling") |
| 2dd24a9c2c8d ("drm/i915/gen11+: First assume next platforms will inherit stuff") |
| 993298af26b1 ("drm/i915: Yet another if/else sort of newer to older platforms.") |
| 13717cef4c1d ("drm/i915/icl: Add icl pipe degamma and gamma support") |
| 9d5441de28e2 ("drm/i915: Populate gamma_mode for all platforms") |
| 051a6d8d3ca0 ("drm/i915: Move LUT programming to happen after vblank waits") |
| 4d8ed54c0447 ("drm/i915: Split color mgmt based on single vs. double buffered registers") |
| 87cefd57c88a ("drm/i915: Pull GAMMA_MODE write out from haswell_load_luts()") |
| 23b03a272c2b ("drm/i915: Constify the state arguments to the color management stuff") |
| 5f4f3e386b36 ("drm/i915: Precompute gamma_mode") |
| 7eb31a0bb2c1 ("drm/i915: Split the gamma/csc enable bits from the plane_ctl() function") |
| e4c0d5314ded ("drm/i915: Apply LUT validation checks to platforms more accurately (v3)") |
| b3c316b0b869 ("drm/i915/icl: Define MOCS table for Icelake") |
| 0fafa2269277 ("drm/i915/lvds: only call intel_lvds_init() on platforms that might have LVDS") |
| 63cb4e641af1 ("drm/i915/crt: split out intel_crt_present() to platform specific setup") |
| 85e2d61e4976 ("drm/i915: Validate userspace-provided color management LUT's (v4)") |
| 129fe7516b23 ("drm/i915/color: switch to kernel types") |
| c4aa2eca319c ("drm/i915/sprite: switch to kernel types") |
| f663b0ca9b7d ("drm/i915/selftests: recreate WA lists inside the selftest") |
| 0258404f9d38 ("drm/i915: start moving runtime device info to a separate struct") |
| 167bc759e823 ("drm/i915: Restrict PSMI context load w/a to Haswell GT1") |
| a489334941d4 ("drm/i915: Fix Cherryview oops on boot") |
| f513ac76530c ("drm/i915/icl: Mind the SFC units when resetting VD or VEBox engines") |
| 57b19d55189b ("drm/i915/icl: Record the valid VDBoxes with SFC capability") |
| cf819eff907a ("drm/i915: replace IS_GEN<N> with IS_GEN(..., N)") |
| 302da0cdf784 ("drm/i915: Use intel_ types more consistently for color management code (v2)") |
| 3abd6143f971 ("drm/i915/selftests: verify_gt_engine_wa() needs rpm wakeref") |
| d15f9cdd59ba ("drm/i915/icl: Do not change reserved registers related to PSR2") |
| 0716931a82b4 ("drm/i915/icl: fix transcoder state readout") |
| 517974992593 ("drm/i915: Allocate a common scratch page") |
| 452420d22d5b ("drm/i915: Fuse per-context workaround handling with the common framework") |
| 69bcdecf1af5 ("drm/i915: Move register white-listing to the common workaround framework") |
| 28d6ccce73be ("drm/i915/selftests: Add tests for GT and engine workaround verification") |
| 094304beb4e1 ("drm/i915: Verify GT workaround state after GPU init") |
| 4a15c75c4246 ("drm/i915: Introduce per-engine workarounds") |
| 25d140faaa25 ("drm/i915: Record GT workarounds in a list") |
| e1bf094b3c75 ("drm/i915: Add HAS_DISPLAY() and use it") |
| 690c318ed8e0 ("drm/i915/icl: add dummy DSI GPIO element execution function") |
| 2eae5d6bfa5f ("drm/i915/icl: Get pipe timings for DSI") |
| 2ca711caeca2 ("drm/i915/icl: Consider DSI for getting transcoder state") |
| c5f9c934936e ("drm/i915/icl: Allocate DSI hosts and imlement host transfer") |
| 972d607c59ed ("drm/i915/icl: Fill DSI ports info") |
| e27580487321 ("drm/i915/icl: Allocate DSI encoder/connector") |
| 70a057b7d425 ("drm/i915/icl: Calculate DPLL params for DSI") |
| b9f78d675230 ("drm/i915/selftests: Fix live_workarounds to actually do resets") |
| 8d2f6e2f2721 ("drm/i915/selftests: Extract spinner code") |
| 83234d13f9fd ("drm/i915: Reorganize plane register writes to make them more atomic") |
| 0e39037b3165 ("drm/i915: Cache the error string") |