blob: f4e07f73df4a1aaa494d4b1e071db93ef57713e7 [file] [log] [blame]
32d38e6cf007 ("drm/i915/tgl/dsi: Enable blanking packets during BLLP for video mode")
35b876db4a42 ("drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming")
5a4712f472bf ("drm/i915/icl: Program HS_TX_TIMEOUT/LP_RX_TIMEOUT/TA_TIMEOUT registers")
9c83ab1bb384 ("drm/i915/icl: Disable portsync mode")
7aa32f7c47c9 ("drm/i915/icl: Disable DDI function")
4769b598b943 ("drm/i915/icl: Put DSI link in ULPS")
522cc3f717ac ("drm/i915/icl: Power down DSI panel")
4e123bd3039d ("drm/i915/icl: Disable DSI transcoders")
d9d996b6ca43 ("drm/i915/icl: Turn OFF panel backlight")
208013157a68 ("drm/i915/icl: Turn ON panel backlight")
32bbc3d450dc ("drm/i915/icl: Wait for header/payload credits release")
c2661638e886 ("drm/i915/icl: Power on DSI panel")
bfee32bfca82 ("drm/i915/icl: Set max return packet size for DSI panel")
303e347cebc3 ("drm/i915/icl: Enable DSI transcoders")
d1aeb5f399d9 ("drm/i915/icl: Configure DSI transcoder timings")
70f4f502c47e ("drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers")
d364dc66e2d5 ("drm/i915/icl: Configure DSI transcoders")
5ffce2546233 ("drm/i915/icl: Define TRANS_DSI_FUNC_CONF register")
ca8fc99f2ac1 ("drm/i915/icl: Get DSI transcoder for a given port")
5fea8645585f ("drm/i915/icl: Program TA_TIMING_PARAM registers")
e72cce531017 ("drm/i915/icl: Program DSI clock and data lane timing params")
67551a703544 ("drm/i915/dsi: abstract dphy parameter init")
2bf3f59daeee ("drm/i915/dsi: refactor bitrate calculations in intel_dsi_vbt_init()")
35c37ade79cd ("drm/i915/icl: Define TA_TIMING_PARAM registers")
33868a91c1d9 ("drm/i915/icl: Define data/clock lanes dphy timing registers")
70a7b83628fa ("drm/i915/icl: Program T_INIT_MASTER registers")
ba3df888be90 ("drm/i915/icl: Enable DDI Buffer")
3f4b9d9d02c6 ("drm/i915/icl: DSI vswing programming sequence")
fc41001d9708 ("drm/i915/icl: Configure lane sequencing of combo phy transmitter")
146cdf3fad9c ("drm/i915/icl: Define T_INIT_MASTER registers")