| 38f5bd23deae ("riscv: Add cache information in AUX vector") |
| b5fca7c55f9f ("riscv: Define AT_VECTOR_SIZE_ARCH for ARCH_DLINFO") |
| baf7cbd94b56 ("riscv: Set more data to cacheinfo") |
| 087958a17658 ("riscv: cacheinfo: Implement cache_get_priv_group with a generic ops structure") |
| 94f9bf118f1e ("RISC-V: Fix of_node_* refcount") |
| f99fb607fb2b ("RISC-V: Use Linux logical CPU number instead of hartid") |
| 6825c7a80f18 ("RISC-V: Add logical CPU indexing for RISC-V") |
| a37d56fc4011 ("RISC-V: Use WRITE_ONCE instead of direct access") |
| 177fae451588 ("RISC-V: Rename im_okay_therefore_i_am to found_boot_cpu") |
| b2f8cfa7ac34 ("RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid") |
| 19ccf29bb18f ("RISC-V: Filter ISA and MMU values in cpuinfo") |
| 566d6c428ead ("RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}") |
