| 39bca3599aab ("drm/amd/display: add a option to force the clock at every mode change.") |
| 290129c25617 ("drm/amd/display: Add CM_BYPASS via debug option") |
| 70f1476a7eed ("drm/amd/display: Add debug option to disable timing sync") |
| a6465d1f3b8f ("drm/amd/display: dcn2 use fixed clocks.") |
| 2131f65581ba ("drm/amd/display: add support for forcing DCFCLK without affecting watermarks") |
| c69dd2d06cdf ("drm/amd/display: Refactor clk_mgr functions") |
| 8712bda45cdc ("drm/amd/display: dcn2 dmcu wait_for_loop update with dispclk.") |
| 97bda0322b8a ("drm/amd/display: Add DSC support for Navi (v2)") |
| 476e955dd679 ("drm/amd/display: Hook DCN2 into amdgpu_dm and expose as config (v2)") |
| 6fbefb84a98e ("drm/amd/display: Add DC core changes for DCN2") |
| 7ed4e6352c16 ("drm/amd/display: Add DCN2 HW Sequencer and Resource") |
| 345429a67c48 ("drm/amd/display: Add DCN2 DWB") |
| f7de96ee8b5f ("drm/amd/display: Add DCN2 DPP") |
| f789b0b82bf0 ("drm/amd/display: Add DCN2 MPC") |
| 2d78b3a177fe ("drm/amd/display: Add DCN2 OPTC") |
| fcee01b9f82d ("drm/amd/display: Add DCN2 clk mgr") |
| ca4d9b3a5a3b ("drm/amd/display: Add DCN2 DIO") |
| 48321c3dde79 ("drm/amd/display: Read soc_bounding_box from gpu_info (v2)") |
| 35c2e91059cb ("drm/amdgpu: parse the new members added by gpu_info ucode v1_1") |
| 109c80ddb40f ("drm/amdgpu: add gpu_info_firmware v1_1 structure for navi10") |
| c5c07cb5435e ("drm/amd/display: Refactor DIO stream encoder") |
| baa1fd7f32f2 ("drm/amd/display: Refactor clk_mgr functions") |
| 961ea20155d7 ("drm/amd/display: Fix type of pp_smu_wm_set_range struct") |
| 8e0546d6c4b1 ("drm/amd/display: Add min_dcfclk_mhz field to bb overrides") |
| 9b93eb475aa9 ("drm/amd/display: move clk_mgr files to right place") |
| e63e2491ad92 ("drm/amd/display: Ensure DRR triggers in BP") |
| 313a9a21ff46 ("drm/amd/display: Add GSL source select registers") |
| dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific") |
| 78cc70b1e47d ("drm/amd/display: Engine-specific encoder allocation") |
| 6476a7c8f031 ("drm/amd/display: Program VTG params after programming Global Sync") |
| 24c18794946a ("drm/amd/display: add null checks and set update flags") |
| 97df424fe7a7 ("drm/amd/display: Drop DCN1_01 guards") |
| d7316ddc610f ("drm/amd/display: Add ASICREV_IS_PICASSO") |
| 88ccdf1d59df ("drm/amd/display: Expose send immediate sdp message interface") |
| b2293ac23776 ("drm/amd/display: move back vbios cmd table for set dprefclk") |
| e7e10c464a48 ("drm/amd/display: stop external access to internal optc sync params") |
| db819940b0ef ("drm/amd/display: move signal type out of otg dlg params") |
| 8dea49605f6e ("drm/amd/display: add support for disconnected eDP panels") |
| 21e471f0850d ("drm/amd/display: Set dispclk and dprefclock directly") |
| 09aef2c48e79 ("drm/amd/display: Compensate for pre-DCE12 BTR-VRR hw limitations. (v3)") |
| a0867053408e ("drm/amd/display: remove deprecated pplib interface") |
| 27eaa4927dc3 ("drm/amd/display: Add power down display on boot flag") |
| f55be0be5b72 ("drm/amd/display: Add profiling tools for bandwidth validation") |
| afcd526b1ba9 ("drm/amd/display: Add fast_validate parameter") |
| c7e557ab46a7 ("drm/amd/display: Clean up locking in dcn*_apply_ctx_for_surface()") |
| c85fc65e2241 ("drm/amd/display: init dc_config before rest of DC init") |
| b4423fd9cf3e ("drm/amd/display: return correct dc_status for dcn10_validate_global") |
| a1e07ba89d49 ("drm/amd/display: Use plane->color_space for dpp if specified") |
| 332c11914a76 ("drm/amd/display: Calculate link bandwidth in a common function") |
| 0de34efc7b5f ("drm/amd/display: fix clk_mgr naming") |
