| 93b96255bd64 ("drm/amd/amdgpu: simplify pa_sc_tile_steering_override check") |
| 6c72c7a03ae5 ("drm/amdgpu: force pa_sc_tile_steering_override to 0 for dimgrey_cavefish") |
| 6c266fb56cb8 ("drm/amdgpu: add gfx support for van gogh (v3)") |
| c5b6c914d2f3 ("drm/amdgpu: enable cp_fw_write_wait for navy_flounder") |
| 8f8463dddcad ("drm/amdgpu: force pa_sc_tile_steering_override to 0 for navy_flounder") |
| c4a8b802869c ("drm/amdgpu: configure navy_flounder gfx according to gfx 10.3") |
| 885eb3fad6ff ("drm/amdgpu: add gfx ip block for navy_flounder") |
| 026c396b41a4 ("drm/amdgpu: add ih ip block for navy_flounder") |
| fc8f07da1f47 ("drm/amdgpu: add gmc ip block for navy_flounder") |
| 8515e0a489e0 ("drm/amdgpu: add common ip block for navy_flounder") |
| d463d8c964dd ("drm/amdgpu/gfx10: add clockgating support for navy_flounder") |
| 650101930405 ("drm/amdgpu/gfx10: add support for navy_flounder firmware") |
| 8db1015b99b2 ("drm/amdgpu/sriov : Use kiq to do tlb invalidation for gfx10 on sriov") |
| 689dede0a0ee ("drm/amdgpu: enable 3D pipe 1 on Sienna_Cichlid") |
| 305401e77bf8 ("drm/amdgpu: force pa_sc_tile_steering_override to 0 for gfx10.3") |
| 263acd471f50 ("drm/amdgpu/gfx10: add gc golden setting for sienna_cichlid") |
| 58139a42dc08 ("drm/amdgpu/gfx10: change register configure for sienna_cichlid") |
| 933c8a93e241 ("drm/amdgpu: add gfx ip block for sienna_cichlid (v3)") |
| 757b3af8ecb4 ("drm/amdgpu: add ih ip block for sienna_cichlid") |
| 0b3df16b5abc ("drm/amdgpu: add gmc ip block for sienna_cichlid") |
| 2e1ba10e9271 ("drm/amdgpu/soc15: add common ip block for sienna_cichlid") |
| 2f7f522722ef ("drm/amdgpu/gfx10: add clockgating support for sienna_cichlid") |
| 6c06333073ac ("drm/amdgpu/gfx10: add support for sienna_cichlid firmware") |
| 43a10b15d442 ("amd/amdgpu: Limit rlcg write registers only for nv12") |
| 4189425d309a ("drm/amdgpu: add SPM golden settings for Navi10(v2)") |
| 1675c3a24d07 ("drm/amdgpu: stop disable the scheduler during HW fini") |
| 2e0cc4d48b91 ("drm/amdgpu: revise RLCG access path") |
| f091c1c70e89 ("drm/amdgpu: disable 3D pipe 1 on Navi1x") |
| 1da7d4a8ab79 ("drm/amdgpu: Write blocked CP registers using RLC on VF") |
| 460c484f2411 ("drm/amdgpu: Initialize SPM_VMID with 0xf (v2)") |
| a5e82d0b9505 ("drm/amdgpu/gfx10: unlock srbm_mutex after queue programming finish") |
| c25edaaf75af ("drm/amdgpu/gfx10: re-init clear state buffer after gpu reset") |
| 387d40fd6fb6 ("drm/amdgpu/gfx10: explicitly wait for cp idle after halt/unhalt") |
| 4effa8dbc117 ("drm/amdgpu/vcn2.5: fix the enc loop with hw fini") |
| 14f43e8f88c5 ("drm/amdgpu: move JPEG2.5 out from VCN2.5") |
| b0f3cd3191cd ("drm/amdgpu: remove unnecessary JPEG2.0 code from VCN2.0") |
| 6ac27241106b ("drm/amdgpu: add JPEG v2.0 function supports") |
| bb0db70f3f75 ("drm/amdgpu: separate JPEG1.0 code out from VCN1.0") |
| 9d9cc9b8fe85 ("drm/amdgpu: add amdgpu_jpeg and JPEG tests") |
| 88a1c40a04de ("drm/amdgpu: add JPEG HW IP and SW structures") |
| a6522a5c6388 ("drm/amdgpu: add dummy read by engines for some GCVM status registers in gfx10") |
| ad02e08e0578 ("drm/amdgpu: Report vram vendor with sysfs (v3)") |
| fd287c8cd248 ("drm/amdgpu/vcn: use amdgpu_ring_test_helper") |
| 631cdbd27e92 ("drm/amdgpu/atomfirmware: simplify the interface to get vram info") |
| bd5520273cea ("drm/amdgpu/atomfirmware: use proper index for querying vram type (v3)") |
| 393993ac0cc9 ("drm/amdgpu/SRIOV: Navi12 SRIOV VF gets GTT base") |
| 9d1b3c78052e ("drm/amdgpu: reserve at least 4MB of VRAM for page tables v2") |
| 3ff985485b29 ("drm/amdgpu: Export function to flush TLB of specific vm hub") |
| 244511f386cc ("drm/amdgpu: simplify and cleanup setting the dma mask") |
| 44e9e7c96c5e ("drm/amdgpu: add ip blocks for navi12") |
