| 9a85eb4d6242 ("clk: tegra: Add support for OSC_DIV fixed clocks") |
| 6b301a059eb2 ("clk: tegra: Add support for Tegra210 clocks") |
| 6929715cf6b9 ("clk: tegra: pll: Add support for PLLMB for Tegra210") |
| dd322f047d22 ("clk: tegra: pll: Add specialized logic for Tegra210") |
| 267b62a96951 ("clk: tegra: pll: Update PLLM handling") |
| 86c679a52294 ("clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate") |
| 407254da291c ("clk: tegra: pll: Add logic for out-of-table rates for T210") |
| d907f4b4a178 ("clk: tegra: pll: Add logic for handling SDM data") |
| 3706b43629f5 ("clk: tegra: pll: Don't unconditionally set LOCK flags") |
| 7db864c9deb2 ("clk: tegra: pll: Simplify clk_enable_path") |
| 6583a6309e83 ("clk: tegra: pll: Add tegra_pll_wait_for_lock to clk header") |
| 385f9adf625f ("clk: tegra: Constify pdiv-to-hw mappings") |
| 8d99704fde54 ("clk: tegra: Format tables consistently") |
| e52d7c04bb39 ("clk: tegra: Miscellaneous coding style cleanups") |
| c4947e364b50 ("clk: tegra: Fix 26 MHz oscillator frequency") |
