| addc80f0bba9 ("drm/i915/tv: Fix adjusted_mode dotclock for interlaced modes") |
| 8a920e24f058 ("drm/i915/tv: Use the scanline counter for timestamps on i965gm TV output") |
| 690157f0a9e7 ("drm/i915/tv: Fix >1024 modes on gen3") |
| e3bb355c7d8b ("drm/i915/tv: Generate better pipe timings for TV encoder") |
| 5023520fd372 ("drm/i915/tv: Use drm_mode_set_name() to name TV modes") |
| 65ddf7f968b8 ("drm/i915/tv: Deobfuscate preferred mode selection") |
| bda5f53206e5 ("drm/i915/tv: Nuke silly 0 initialzation of xpos/ypos") |
| 6801603d3d7d ("drm/i915/tv: Fix interlaced ysize calculation") |
| 204474a6b859 ("drm/i915: Pass down rc in intel_encoder->compute_config()") |
| f6bff60e927b ("drm/i915/icl: Fix HPD handling for TypeC legacy ports") |
| e845f099f1c6 ("drm/i915/dsc: Add Per connector debugfs node for DSC support/enable") |
| cf819eff907a ("drm/i915: replace IS_GEN<N> with IS_GEN(..., N)") |
| d15f9cdd59ba ("drm/i915/icl: Do not change reserved registers related to PSR2") |
| 517974992593 ("drm/i915: Allocate a common scratch page") |
| 69bcdecf1af5 ("drm/i915: Move register white-listing to the common workaround framework") |
| 28d6ccce73be ("drm/i915/selftests: Add tests for GT and engine workaround verification") |
| 094304beb4e1 ("drm/i915: Verify GT workaround state after GPU init") |
| 4a15c75c4246 ("drm/i915: Introduce per-engine workarounds") |
| 25d140faaa25 ("drm/i915: Record GT workarounds in a list") |
| e1bf094b3c75 ("drm/i915: Add HAS_DISPLAY() and use it") |
| d04afb150172 ("drm/i915/icl: Add DSI encoder compute config hook") |
| ab8411483a3e ("drm/i915/icl: Get HW state for DSI encoder") |
| 8327af281d29 ("drm/i915/icl: Add get config functionality for DSI") |
| e27580487321 ("drm/i915/icl: Allocate DSI encoder/connector") |
| b9f78d675230 ("drm/i915/selftests: Fix live_workarounds to actually do resets") |
| 8d2f6e2f2721 ("drm/i915/selftests: Extract spinner code") |
| 240999cf339f ("i915/dp/fec: Add fec_enable to the crtc state.") |
| 168243c18010 ("drm/i915/dsc: Define & Compute VESA DSC params") |
| a4a157777c80 ("drm/i915/dp: Compute DSC pipe config in atomic check") |
| 7b610f1fbed2 ("drm/i915/dp: Add DSC params and DSC config to intel_crtc_state") |
| ff43bc379e16 ("drm/i915: Move ddb/wm programming into plane update/disable hooks on skl+") |
| 51de9c6d2559 ("drm/i915: Don't pass dev_priv around so much") |
| 8315847bf4df ("drm/i915: Clean up skl+ vs. icl+ watermark computation") |
| 6a3c910b081d ("drm/i915: Pass the entire skl_plane_wm to skl_compute_transition_wm()") |
| 14a43062b903 ("drm/i915: Remove some useless zeroing on skl+ wm calculations") |
| ce110ec311e9 ("drm/i915: Fix latency==0 handling for level 0 watermark on skl+") |
| 83234d13f9fd ("drm/i915: Reorganize plane register writes to make them more atomic") |
| 0e39037b3165 ("drm/i915: Cache the error string") |
| 95fd94a645f7 ("drm/i915: avoid rebuilding i915_gpu_error.o on version string updates") |
| 8f19b401a6fc ("drm/i915: Make CHICKEN_TRANS reg not depend on enum value") |
| fb6f0b64e455 ("drm/i915: Prevent machine hang from Broxton's vtd w/a and error capture") |
| 03981c6ebec4 ("drm/i915: Disable LP3 watermarks on all SNB machines") |
| cb8ef723ab81 ("drm/i915/gen9_bc: Work around DMC bug zeroing power well requests") |
| 745aa6cdee6b ("drm/i915: Fix icl workarounds whitespaces") |
| 85f04aa569ad ("drm/i915: Deduplicate register definition for GAMW_ECO_DEV_RW_IA") |
| ca0026790efa ("drm/i915: Always write both TILEOFF and LINOFF plane registers") |
| d26592c601ec ("drm/i915: Remove pointless goto fail") |
| 8e2b4dffeca0 ("drm/i915: Handle -EDEADLK from ironlake_check_fdi_lanes()") |
| 53cc68803668 ("drm/i915: Generalize skl_ddb_allocation_overlaps()") |
| 07464c7c0cf7 ("drm/i915: Clean up skl+ PLANE_POS vs. scaler handling") |