| ba0eb9d57a37 ("clk: tegra: Use NULL for pointer initialization") |
| 89e423c3f14c ("clk: tegra: Add la clock for Tegra210") |
| bc2e4d2986e9 ("clk: tegra: Fix sor1_out clock implementation") |
| e745f992cf4b ("clk: tegra: Rework pll_u") |
| 3843832fc8ca ("clk: tegra: Handle UTMIPLL IDDQ") |
| 24c3ebef1ab6 ("clk: tegra: Add aclk") |
| 319af7975c9f ("clk: tegra: Define Tegra210 DMIC sync clocks") |
| bfa34832df1f ("clk: tegra: Add CEC clock") |
| 8dce89a1c2cf ("clk: tegra: Don't warn for PLL defaults unnecessarily") |
| 34ac2c278b30 ("clk: tegra: Fix ISP clock modelling") |
| 9326947f2215 ("clk: tegra: Fix pll_a1 iddq register, add pll_a1") |
| 15d68e8c2e95 ("clk: tegra: Initialize UTMI PLL when enabling PLLU") |
| 74d3ba0b6f1b ("clk: tegra: Micro-optimize Tegra210 clock setup") |
| 2e34c2ac16ee ("clk: tegra: Make sor_safe the parent of dpaux and dpaux1") |
| c1273af4b921 ("clk: tegra: Squash sor1 safe/brick/src into a single mux") |
| a91bb605ec5f ("clk: tegra: Add sor_safe clock") |
| eede7113aabd ("clk: tegra: dpaux and dpaux1 are fixed factor clocks") |
| 98c4b3661b5a ("clk: tegra: Add dpaux1 clock") |
| 3d0f4e5f7a7c ("clk: tegra: Use correct parent for dpaux clock") |
| 3358d2d9f47a ("clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs") |
| fd360e20844a ("clk: tegra: Fix sparse warnings for functions not declared as static") |
| 2d5b6cf84a17 ("clk: tegra: Use definition for pll_u override bit") |
| 29569941688c ("clk: tegra: Add the APB2APE audio clock on Tegra210") |
| 14050118afee ("clk: tegra: Remove improper flags for lock_enable") |
| 6b301a059eb2 ("clk: tegra: Add support for Tegra210 clocks") |
| 6929715cf6b9 ("clk: tegra: pll: Add support for PLLMB for Tegra210") |
| dd322f047d22 ("clk: tegra: pll: Add specialized logic for Tegra210") |
| 267b62a96951 ("clk: tegra: pll: Update PLLM handling") |
| 86c679a52294 ("clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate") |
| 407254da291c ("clk: tegra: pll: Add logic for out-of-table rates for T210") |
| d907f4b4a178 ("clk: tegra: pll: Add logic for handling SDM data") |
| 3706b43629f5 ("clk: tegra: pll: Don't unconditionally set LOCK flags") |
| 7db864c9deb2 ("clk: tegra: pll: Simplify clk_enable_path") |
| 6583a6309e83 ("clk: tegra: pll: Add tegra_pll_wait_for_lock to clk header") |
| dc37fec48314 ("clk: tegra: periph: Add new periph clks and muxes for Tegra210") |
| 385f9adf625f ("clk: tegra: Constify pdiv-to-hw mappings") |
| 8d99704fde54 ("clk: tegra: Format tables consistently") |
| e52d7c04bb39 ("clk: tegra: Miscellaneous coding style cleanups") |
| c4947e364b50 ("clk: tegra: Fix 26 MHz oscillator frequency") |
| 1d15cb9ce9a2 ("clk: tegra: Add Tegra210 device tree binding") |
