| bf59ebbeac1f ("bus: ti-sysc: re-order reset and main clock controls") |
| 4345f0dc015d ("bus: ti-sysc: rework the reset handling") |
| b6036314436b ("bus: ti-sysc: re-order the clkdm control around reset handling") |
| 8383e25994ef ("bus: ti-sysc: Add support for disabling module without legacy mode") |
| 2b2f7def058a ("bus: ti-sysc: Add support for missing clockdomain handling") |
| d59b60564cbf ("bus: ti-sysc: Add generic enable/disable functions") |
| b11c1ea1f636 ("bus: ti-sysc: Move rstctrl reset to happen later") |
| 93de83a21e76 ("bus: ti-sysc: Manage clocks for the interconnect target module in all cases") |
| a3e92e7b32f2 ("bus: ti-sysc: Allocate mdata as needed and do platform data based init later") |
| 1a5cd7c23cc5 ("bus: ti-sysc: Enable all clocks directly during init to read revision") |
| d878970f6ce1 ("bus: ti-sysc: Add separate functions for handling clocks") |
| ff43728c4aa2 ("bus: ti-sysc: Move legacy platform data idling into separate functions") |
| 386cb76681ca ("bus: ti-sysc: Handle missed no-idle property in addition to no-idle-on-init") |
| b57250fa5eb3 ("ARM: OMAP2+: Allocate struct omap_hwmod based on dts data") |
| 513a4abb19d5 ("ARM: OMAP2+: Prepare class allocation for dynamically allocated modules") |
| 798bd175ab0d ("ARM: OMAP2+: Make interconnect target module allocation functions static") |
| f5e80203dadc ("bus: ti-sysc: Just use SET_NOIRQ_SYSTEM_SLEEP_PM_OPS") |
| 40d9f9124822 ("bus: ti-sysc: Defer suspend as needed") |
