| f1c7a36b05ed ("drm/i915: Use ddi_update_pipe in intel_dp_mst") |
| cafac5a98361 ("drm/i915/dp: Add compute routine for DP PSR VSC SDP") |
| 1bf3657c03dd ("drm/i915: Program DP SDPs with computed configs") |
| 1b404b7dbb10 ("drm/i915/dp: Read out DP SDPs") |
| af67009c1439 ("drm/i915/dp: use struct drm_device based logging") |
| ede9771d7f84 ("drm/i915: Pass atomic state to encoder hooks") |
| 589a4cd6cc43 ("drm/i915: Move TRANS_DDI_FUNC_CTL2 programming where it belongs") |
| 0c1abaa7fbfb ("drm: Constify adjusted_mode a bit") |
| 47bdb1caba0b ("drm/i915/ddi: use struct drm_device based logging") |
| 13ea6db2cf24 ("drm/i915/edp: Ignore short pulse when panel powered off") |
| 03c761b00c87 ("drm/i915/dp: Add writing of DP SDPs") |
| d1eed96dcb60 ("drm/i915/dp: Add compute routine for DP HDR Metadata Infoframe SDP") |
| 9799c4c3b76e ("drm/i915/dp: Add compute routine for DP VSC SDP") |
| 2c1816af090d ("drm/i915/display: Decrease log level") |
| b50a1aa6e1e9 ("drm/i915/dp: Compute port sync crtc states post compute_config()") |
| 919e4f07392d ("drm/i915/display: Set TRANS_DDI_MODE_SELECT to default value when clearing DDI select") |
| 5758e0738458 ("drm/i915/hdcp: move update pipe code to hdcp") |
| 6dcde04706d8 ("drm/i915: Move linetime wms into the crtc state") |
| 0560b0c6b36c ("drm/i915: Polish WM_LINETIME register stuff") |
| 21fd23ac222f ("drm/i915: move pipe, pch and vblank enable to encoders on DDI platforms") |
| dc008bf0aa09 ("drm/i915/display: use intel_de_*() functions for register access") |
| f7960e7f8f24 ("drm/i915/ddi: use intel_de_*() functions for register access") |
| cd49f8180681 ("drm/i915/display: conversion to new struct drm_device logging macros.") |
| c5c772cf8d7c ("drm/i915/dc3co: Avoid full modeset when EXITLINE needs to be changed") |
| 691313ea6214 ("drm/i915: Move encoder variable to tighter scope") |
| b7d02c3a124d ("drm/i915: Pass intel_encoder to enc_to_*()") |
| 43a6d19cace6 ("drm/i915: Pass intel_connector to intel_attached_*()") |
| 7829c92b913f ("drm/i915: Fix MST disable sequence") |
| 60c6a14b489b ("drm/i915/display: Force the state compute phase once to enable PSR") |
| 2dfbf9d2873a ("drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine") |
| 5cf15dfca91c ("drm/i915: Add debug message for FB plane[0].offset!=0 error") |
| d156135e6a54 ("drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned") |
| a3d9382bd439 ("drm/i915/dp: Disable Port sync mode correctly on teardown") |
| aee40639cdc3 ("drm/i915/dp: Make port sync mode assignments only if all tiles present") |
| 9eae5e27be4a ("drm/i915: prefer 3-letter acronym for ironlake") |
| f6df4d46bf1e ("drm/i915: prefer 3-letter acronym for skylake") |
| 1e98f88cea0f ("drm/i915: prefer 3-letter acronym for haswell") |
| 1e1a139d62d1 ("drm/i915: Extend WaDisableDARBFClkGating to icl,ehl,tgl") |
| c59053dc58fa ("drm/i915/dp: Fix MST disable sequence") |
| 6671c367a9be ("drm/i915/tgl: Select master transcoder for MST stream") |
| ee36c7c0c837 ("drm/i915/display: Share intel_connector_needs_modeset()") |
| 4941f35b48f7 ("drm/i915: Make sure CCS YUV semiplanar format checks work") |
| 71df86f0fbf5 ("drm/i915/tgl: Make sure FBs have a correct CCS plane stride") |
| b3e57bccd68a ("drm/i915/tgl: Gen-12 render decompression") |
| e7af90945794 ("drm/i915: Add helpers to select correct ccs/aux planes") |
| 13f2cb9a2800 ("drm/i915: Extract framebufer CCS offset checks into a function") |
| 86f236bbbd88 ("drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment") |
| d6f970f0dad6 ("drm/i915/display: fix phy name") |
| 5956f44028f5 ("drm/i915/display: move clk off sanitize to its own function") |
| 773b4b54351c ("drm/i915: Move stuff from haswell_crtc_disable() into encoder .post_disable()") |
