| f64668f9aab6 ("drm/amdgpu: only use one gfx pipe for Sienna_Cichlid") |
| 689dede0a0ee ("drm/amdgpu: enable 3D pipe 1 on Sienna_Cichlid") |
| 83a0c342e04a ("drm/amdgpu: update the num of queue per pipe for mec on sienna_cichlid") |
| f091c1c70e89 ("drm/amdgpu: disable 3D pipe 1 on Navi1x") |
| a5e82d0b9505 ("drm/amdgpu/gfx10: unlock srbm_mutex after queue programming finish") |
| 9ff3dba6d68d ("drm/amdgpu/gfx10: set number of me(c)/pipe/queue for navi12") |
| 0c090023c639 ("drm/amdgpu: add me/mec configurations for navi14") |
| 687ac4a702ea ("drm/amdgpu: drop copy/paste leftover to fix big endian") |
| a644d85a5cd4 ("drm/amdgpu: add gfx v10 implementation (v10)") |
| 1b3f6bc96883 ("drm/amdgpu: increase the MAX ring number") |
