| 1ba1014db258 ("drm/i915/edp/jsl: Update vswing table for HBR and HBR2") |
| 24ea098b7c0d ("drm/i915/jsl: Split EHL/JSL platform info and PCI ids") |
| 0642c2b83749 ("drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D") |
| cf72562094a0 ("drm/i915/display/ehl: Limit eDP to HBR2") |
| a621860a5eb8 ("drm/i915: Plumb crtc_state to link training") |
| 6a41121f0550 ("drm/i915: Split TGL DKL PHY buf trans per output type") |
| 4669f5c2b7ed ("drm/i915: Split TGL combo PHY buf trans per output type") |
| ba30075d8d84 ("drm/i915: Split EHL combo PHY buf trans per output type") |
| 5ee3e1daa816 ("drm/i915: Split ICL MG PHY buf trans per output type") |
| 6ed9aefa69fc ("drm/i915: Split ICL combo PHY buf trans per output type") |
| 193af12cd681 ("drm/i915: Shove the PHY test into the hotplug work") |
| 7ac469a0f7c6 ("drm/i915: Make intel_dp_process_phy_request() static") |
| 945b18fb4803 ("drm/i915: Fix TGL DKL PHY DP vswing handling") |
| b7feffd584ba ("drm/i915: Configure DP 1.3+ protocol converted HDMI mode") |
| 400d4953f1f4 ("drm/i915/pll: Centralize PLL_ENABLE register lookup") |
| da51e4bafdfa ("drm/i915: Introduce HPD_PORT_TC<n>") |
| 03c7e4f1190e ("drm/i915: Move hpd_pin setup to encoder init") |
| a52bfcdd806f ("drm/i915: Nuke the redundant TC/TBT HPD bit defines") |
| 2a498ab49256 ("drm/i915/display/ehl: Use EHL DP tables for eDP ports without low power support") |
| a8c90bc11990 ("drm/i915/display/tgl: Use TGL DP tables for eDP ports without low power support") |
| 25a322fde74f ("drm/i915: Update TGL and RKL HuC firmware versions") |
| 04dfb1acbae6 ("drm/i915/tgl: Add new voltage swing table") |
| ddff9a602e5e ("drm/i915/rkl: Handle HTI") |
| e66f609baeee ("drm/i915/rkl: Add DPLL4 support") |
| 81619f4a75ed ("drm/i915/display: Implement HOBL") |
| 963501bdd094 ("drm/i915/ddi: Don't frob the DP link scramble disabling flag") |
| a133c6988f70 ("drm/i915: WARN if max vswing/pre-emphasis violates the DP spec") |
| f0e86e052097 ("drm/i915/display: Remove port and phy from voltage swing functions") |
| a8143150faa7 ("drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder") |
| 9b413f011c2c ("drm/i915/sseu: Move sseu detection and dump to intel_sseu") |
| d0eb6866879f ("drm/i915: Introduce gt_init_mmio") |
| 792592e72aba ("drm/i915: Move the engine mask to intel_gt_info") |
| f6beb3810077 ("drm/i915: Move engine-related mmio init to engines_init_mmio") |
| 242613af557f ("drm/i915: Use the gt in HAS_ENGINE") |
| fdeb6d02686f ("drm/i915: Convert device_info to uncore/de_read") |
| 52797a8e8529 ("drm/i915/ehl: Add new PCI ids") |
| 7801f3b792b0 ("drm/i915/display: prefer dig_port to reference intel_digital_port") |
| fc6200948275 ("drm/i915/icl+: Simplify combo/TBT PLL calculation call-chain") |
| 0ba7ffea2d11 ("drm/i915/display: remove alias to dig_port") |
| b08239b2f471 ("drm/i915: HDCP: retry link integrity check on failure") |
| 3625a1f5bf6b ("drm/i915: Fix DP_TRAIN_MAX_{PRE_EMPHASIS,SWING}_REACHED handling") |
| 94641eb6c696 ("drm/i915/display: Fix the encoder type check") |
| c980216dd224 ("drm/i915/icl: Disable DIP on MST ports with the transcoder clock still on") |
| 2cf122070c56 ("drm/i915/rkl: Update TGP's pin mapping when paired with RKL") |
| 24d2fc3d530e ("drm/i915/rkl: Disable PSR2") |
| aefaa1f452ab ("drm/i915/rkl: Setup ports/phys") |
| 9fa6769952ee ("drm/i915/tgl: Add HBR and HBR2+ voltage swing table") |
| e2db55244e0f ("drm/i915: Replace some hand rolled max()s") |
| f6adb5f06195 ("drm/i915: Reverse preemph vs. voltage swing preference") |
| 53de0a20c8cd ("drm/i915: Add {preemph,voltage}_max() vfuncs") |
