| 230edf78ed4b ("drm/i915: Add plane .{min,max}_width() and .max_height() vfuncs") |
| d24f1341a63c ("drm/i915: Apply Wa_14011264657:gen11+") |
| 5331889b5ffb ("drm/i915/fbc: Fix fence_y_offset handling") |
| 765e7cd9a6fd ("drm/i915/display: Do not write in removed FBC fence registers") |
| 6a0e032fb524 ("drm/i915/display/fbc: Make WARN* drm specific where drm_priv ptr is available") |
| aa93f4fd7c89 ("drm/i915/fbc: use intel_de_*() functions for register access") |
| cd49f8180681 ("drm/i915/display: conversion to new struct drm_device logging macros.") |
| 691313ea6214 ("drm/i915: Move encoder variable to tighter scope") |
| d54151c5c8c0 ("drm/i915/fbc: Add fbc tracepoints") |
| 43a6d19cace6 ("drm/i915: Pass intel_connector to intel_attached_*()") |
| 2dfbf9d2873a ("drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine") |
| 5cf15dfca91c ("drm/i915: Add debug message for FB plane[0].offset!=0 error") |
| d156135e6a54 ("drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned") |
| aee40639cdc3 ("drm/i915/dp: Make port sync mode assignments only if all tiles present") |
| 6671c367a9be ("drm/i915/tgl: Select master transcoder for MST stream") |
| ee36c7c0c837 ("drm/i915/display: Share intel_connector_needs_modeset()") |
| 4941f35b48f7 ("drm/i915: Make sure CCS YUV semiplanar format checks work") |
| 71df86f0fbf5 ("drm/i915/tgl: Make sure FBs have a correct CCS plane stride") |
| b3e57bccd68a ("drm/i915/tgl: Gen-12 render decompression") |
| e7af90945794 ("drm/i915: Add helpers to select correct ccs/aux planes") |
| 13f2cb9a2800 ("drm/i915: Extract framebufer CCS offset checks into a function") |
| 86f236bbbd88 ("drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment") |
| 979e94c1d64a ("drm/i915: Introduce intel_crtc_state_reset()") |
| 6643453987c4 ("drm/i915: Introduce intel_crtc_{alloc,free}()") |
| f44bfa7fbfbb ("drm/i915: s/intel_crtc/crtc/ in intel_crtc_init()") |
| fbacb15ea814 ("drm/i915/dsc: add basic hardware state readout support") |
| 2d15f3925a4b ("drm/i915/dsc: add support for computing and writing PPS for DSI encoders") |
| e10ad9c69746 ("drm/i915/fbc: Reallocate cfb if we need more of it") |
| 6252bb78fcc3 ("drm/i915/fbc: Start using flip nuke") |
| c866a0e41640 ("drm/i915/fbc: Nuke fbc.enabled") |
| 31ce20c24721 ("drm/i915/fbc: s/gen9 && !glk/gen9_bc || bxt/") |
| 30016696c2e0 ("drm/i915/fbc: Make fence_id optional for i965gm") |
| 97a978e2d3a0 ("drm/i915/fbc: Store fence_id directly in fbc cache/params") |
| 8bdbe1befd9d ("drm/i915/fbc: Track plane visibility") |
| 6f745ba696fd ("drm/i915/fbc: Precompute gen9 cfb stride w/a") |
| 644398586f00 ("drm/i915/fbc: Remove the FBC_RT_BASE setup for ILK/SNB") |
| fb2d8e0cd4d7 ("drm/i915/fbc: Nuke bogus single pipe fbc1 restriction") |
| ad457191015a ("drm/i915/display: Refactor intel_commit_modeset_disables()") |
| 3ca8f1918883 ("drm/i915/display/tgl: Fix the order of the step to turn transcoder clock off") |
| bee43ca4c1cc ("drm/i915: Clean up intel_{pre,post}_plane_update()") |
| 0e75fb8c03aa ("drm/i915: s/pipe_config/new_crtc_state/ intel_{pre,post}_plane_update()") |
| 60aca5741a69 ("drm/i915: Pass dev_priv to ilk_disable_lp_wm()") |
| d2432796dc72 ("drm/i915: Clean up arguments to nv12/scaler w/a funcs") |
| 78eaaba3cd78 ("drm/i915/display/mst: Move DPMS_OFF call to post_disable") |
| 50a7efb280a8 ("drm/i915/dp: Power down sink before disable pipe/transcoder clock") |
| e815aff59dcf ("drm/i915/display: Check the old state to find port sync slave") |
| 56273062e760 ("drm/i915: Switch intel_crtc_disable_noatomic() to intel_ types") |
| 7451a074bf2f ("drm/i915: Change .crtc_enable/disable() calling convention") |
| 502d871459d2 ("drm/i915: s/pipe_config/new_crtc_state/ in .crtc_enable()") |
| e44c84a14469 ("drm/i915: s/intel_crtc/crtc/ in .crtc_enable() and .crtc_disable()") |
