| 3d702d06cb3c ("drm/i915/tgl: Implement WAs 18011464164 and 22010931296") |
| 63d0f3ea8ebb ("drm/i915/tgl: Make Wa_14010229206 permanent") |
| b592322f5092 ("drm/i915/tgl: Make Wa_1606700617 permanent") |
| 50148a25f841 ("drm/i915/tgl: Move and restrict Wa_1408615072") |
| d55204d3f829 ("drm/i915/tgl: Add note about Wa_1607063988") |
| f2097beed59e ("drm/i915/tgl: Extend Wa_1606931601 for all steppings") |
| 52c2e4e6f12c ("drm/i915/tgl: Add Wa_1409085225, Wa_14010229206") |
| ec1e12645ff3 ("drm/i915/tgl: Implement Wa_1409804808") |
| 3873fd1a43c7 ("drm/i915: Use engine wa list for Wa_1607090982") |
| 0db1a5f8706a ("drm/i915: Implement Wa_1607090982") |
| 561db8296d8b ("drm/i915: Disable tesselation clock gating on tgl A0") |
| ff690b2111ba ("drm/i915/tgl: Implement Wa_1604555607") |
| 5ba2bb587d89 ("drm/i915/tgl: Wa_1606679103") |
| 99db8c59e056 ("drm/i915/tgl: Wa_1607030317, Wa_1607186500, Wa_1607297627") |
| 79bfa607e60f ("drm/i915/tgl: Wa_1607138336") |
| 99739f9431f9 ("drm/i915/tgl: Keep FF dop clock enabled for A0") |
| 1c757497096f ("drm/i915/tgl: Implement Wa_1409142259") |
| 5d86923060fc ("drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating") |
