| 4a3a1dc02fc3 ("drm/amd/display: Initialize num_pkrs on VANGOGH.") |
| 2a4112050451 ("drm/amd/display: Add DCN302 support in amdgpu_dm (v2)") |
| 469989ca4cb3 ("drm/amd/display: Add dcn3.01 support to DM") |
| a6c5308f2a7a ("drm/amd/display: add DC support for navy flounder") |
| 5404f073595a ("drm/amdgpu: add virtual display support for navy_flounder.") |
| 885eb3fad6ff ("drm/amdgpu: add gfx ip block for navy_flounder") |
| 026c396b41a4 ("drm/amdgpu: add ih ip block for navy_flounder") |
| fc8f07da1f47 ("drm/amdgpu: add gmc ip block for navy_flounder") |
| 8515e0a489e0 ("drm/amdgpu: add common ip block for navy_flounder") |
| 790373245ee6 ("drm/amd/display: Add DCN3 Support in DM (v2)") |
| 81d9bfb8c526 ("drm/amdgpu/dc: Add missing Sienna_Cichlid chip id") |
| 689dede0a0ee ("drm/amdgpu: enable 3D pipe 1 on Sienna_Cichlid") |
| 933c8a93e241 ("drm/amdgpu: add gfx ip block for sienna_cichlid (v3)") |
| 757b3af8ecb4 ("drm/amdgpu: add ih ip block for sienna_cichlid") |
| 0b3df16b5abc ("drm/amdgpu: add gmc ip block for sienna_cichlid") |
| 2e1ba10e9271 ("drm/amdgpu/soc15: add common ip block for sienna_cichlid") |
| 1cfbbddead0a ("drm/amd/display: add addition dc type to translate to dmub fw type") |
| 43a10b15d442 ("amd/amdgpu: Limit rlcg write registers only for nv12") |
| d1ebfdd8d0fc ("drm/amd/display: Unify psr feature flags") |
| efc3ec87a937 ("drm/amd/display: Remove unused defines") |
| 1675c3a24d07 ("drm/amdgpu: stop disable the scheduler during HW fini") |
| c38cc6770fd5 ("drm/amd/display: differentiate vsc sdp colorimetry use criteria between MST and SST") |
| 3b58f22e938b ("drm/amd/display: Remove PSR dependency on swizzle mode") |
| 2e0cc4d48b91 ("drm/amdgpu: revise RLCG access path") |
| f091c1c70e89 ("drm/amdgpu: disable 3D pipe 1 on Navi1x") |
| 1da7d4a8ab79 ("drm/amdgpu: Write blocked CP registers using RLC on VF") |
| 460c484f2411 ("drm/amdgpu: Initialize SPM_VMID with 0xf (v2)") |
| 9dac88d8792a ("drm/amd/display: Add driver support for enabling PSR on DMCUB") |
| 115c7e7f0501 ("drm/amd/display: Add psr get_state call") |
| 8eb85cb5ada1 ("drm/amd/display: Hookup psr set version call") |
| 96577cf82a13 ("drm/amd/display: linux enable oled panel support dc part") |
| fbbd3f8f6b8f ("drm/amd/display: Add GPINT handler interface") |
| d4b8573ef05a ("drm/amd/display: Add set psr version message") |
| bae9c49bf070 ("drm/amd/display: Only program surface flip for video plane via dmcub") |
| 8547058b17f1 ("drm/amd/display: Add monitor patch for AUO dpcd issue") |
| 5adc673c775c ("drm/amd/display: Fix DMUB PSR command IDs") |
| 22aa56145f71 ("drm/amd/display: Refactor surface flip programming") |
| ec256f449c07 ("drm/amd/display: DMCUB FW Changes to support PSR") |
| 8c0192533c39 ("drm/amd/display: programing surface flip by dmcub.") |
| 4c1a1335dfe0 ("drm/amd/display: Driverside changes to support PSR in DMCUB") |
| 1295524e6fee ("drm/amd/display: Soft reset DMUIF during DMUB reset") |
| b7408a06733f ("drm/amd/display: Flush framebuffer data before passing to DMCUB") |
| 5d593d682ffa ("drm/amd/display: Reorder detect_edp_sink_caps before link settings read.") |
| cf27a6d15d95 ("drm/amd/display: update chroma viewport wa") |
| 01c229d977e0 ("drm/amd/display: Get DMUB registers from ASIC specific structs") |
| 6b5d7730d226 ("drm/amd/display: Add wait for flip not pending on pipe unlock") |
| ddba76274fd5 ("drm/amd/display: Limit NV12 chroma workaround") |
| d4bbcecb5962 ("drm/amd/display: Split DMUB cmd type into type/subtype") |
| 1ba2a4830571 ("drm/amd/display: Disable chroma viewport w/a when rotated 180 degrees") |
| 3c465370f20a ("drm/amd/display: Only wait for DMUB phy init on dcn21") |
