| 693260cf23f9 ("drm/i915/rkl: Add new cdclk table") |
| 0fde0b1daac9 ("drm/i915/tgl: Update cdclk voltage level settings") |
| 9d5fd37ed7e2 ("drm/i915/ehl: Update port clock voltage level requirements") |
| d2f429ebb977 ("drm/i915: Add calc_voltage_level display vfunc") |
| 751a93a15cde ("drm/i915: Consolidate {bxt,cnl,icl}_uninit_cdclk") |
| 1cbcd3b4b168 ("drm/i915: Combine bxt_set_cdclk and cnl_set_cdclk") |
| 736da8112fee ("drm/i915: Use literal representation of cdclk tables") |
| 71dc367e2bc3 ("drm/i915: Consolidate bxt/cnl/icl cdclk readout") |
| 71cd86cfaa12 ("drm/i915/tgl: Use refclk/2 as bypass frequency") |
| 3d1da92baffe ("drm/i915: Add 324mhz and 326.4mhz cdclks for gen11+") |
| 385ba629aa1c ("drm/i915: Allow /2 CD2X divider on gen11+") |
| d06a79d33e0f ("drm/i915: Use enum pipe instead of crtc index to track active pipes") |
