| 94d52a355f19 ("drm/amdgpu: update golden setting for sienna_cichlid") |
| 998d76368dff ("drm/amdgpu: update golden setting for sienna_cichlid") |
| 5fe19ce8e48d ("drm/amdgpu: add function to program pbb mode for sienna cichlid") |
| 72ca82c7d218 ("drm/amdgpu: disable gpa mode for direct loading") |
| 04af75ef38c9 ("drm/amdgpu: update golden setting for sienna_cichlid") |
| 0f7ee0575097 ("drm/amdgpu: add cp firmware backdoor loading triger") |
| 263acd471f50 ("drm/amdgpu/gfx10: add gc golden setting for sienna_cichlid") |
| 58139a42dc08 ("drm/amdgpu/gfx10: change register configure for sienna_cichlid") |
| 933c8a93e241 ("drm/amdgpu: add gfx ip block for sienna_cichlid (v3)") |
| 757b3af8ecb4 ("drm/amdgpu: add ih ip block for sienna_cichlid") |
| 0b3df16b5abc ("drm/amdgpu: add gmc ip block for sienna_cichlid") |
| 2e1ba10e9271 ("drm/amdgpu/soc15: add common ip block for sienna_cichlid") |
| 43a10b15d442 ("amd/amdgpu: Limit rlcg write registers only for nv12") |
| f77c9aff85ca ("drm/amdgpu: Fix per-IB secure flag GFX hang") |
| 0bb5d5b03f78 ("drm/amdgpu: Move to a per-IB secure flag (TMZ)") |
| c6252390fccd ("drm/amdgpu: implement TMZ accessor (v3)") |
| 8fb2e01a1ed8 ("drm/amdgpu: enable TMZ bit in FRAME_CONTROL for gfx10") |
| 04379e9b0489 ("drm/amdgpu: fix up for amdgpu_tmz.c and removal of drm/drmP.h") |
| 4cd24494cc87 ("drm/amdgpu: set TMZ bits in PTEs for secure BO (v4)") |
| cb5fae143d79 ("drm/amdgpu: job is secure iff CS is secure (v5)") |
| 8350361d2d75 ("drm/amdgpu: expand the context control interface with trust flag") |
| 155748c912e7 ("drm/amdgpu: expand the emit tmz interface with trusted flag") |
| 01a8dcec1a08 ("drm/amdgpu: add function to check tmz capability (v4)") |
| ae60305ac04f ("drm/amdgpu: add amdgpu_tmz data structure") |
| 5420819401cc ("drm/amdgpu: request reg_val_offs each kiq read reg") |
| b2d92682ff6a ("drm/amdgpu: add SPM golden settings for Navi12") |
| a900f562c8b1 ("drm/amdgpu: add SPM golden settings for Navi14") |
| 4189425d309a ("drm/amdgpu: add SPM golden settings for Navi10(v2)") |
| 1675c3a24d07 ("drm/amdgpu: stop disable the scheduler during HW fini") |
| bd607166af7f ("drm/amdgpu: Enable reading FRU chip via I2C v3") |
| 2e0cc4d48b91 ("drm/amdgpu: revise RLCG access path") |
| 552b80d7409d ("drm/amdgpu: remove unused functions") |
| 1da7d4a8ab79 ("drm/amdgpu: Write blocked CP registers using RLC on VF") |
| 460c484f2411 ("drm/amdgpu: Initialize SPM_VMID with 0xf (v2)") |
| 89510a2737ae ("drm/amdgpu/sriov: Use kiq to copy the gpu clock") |
| d33a99c4b636 ("drm/amdgpu: provide a generic function interface for reading/writing register by KIQ") |
| bdf84a80e0ce ("drm/amdgpu: Create generic DF struct in adev") |
| bdbe90f04d24 ("drm/amdgpu/gmc: move invaliation bitmap setup to common code") |
| e3c00faa7a3d ("drm/amdgpu: Remove unneeded variable 'ret' in amdgpu_device.c") |
| 79c4c8ea9130 ("drm/amdgpu: add check before enabling/disabling broadcast mode") |
| 7c868b592d5c ("drm/amdgpu: not remove sysfs if not create sysfs") |
| c25edaaf75af ("drm/amdgpu/gfx10: re-init clear state buffer after gpu reset") |
| 387d40fd6fb6 ("drm/amdgpu/gfx10: explicitly wait for cp idle after halt/unhalt") |
| 6ae6c7d404ec ("drm/amdgpu: start to disentangle boco from runtime pm") |
| 31af062acfbd ("drm/amdgpu: rename amdgpu_device_is_px to amdgpu_device_supports_boco (v2)") |
| a69cba42b11a ("drm/amdgpu: add a amdgpu_device_supports_baco helper") |
| 4effa8dbc117 ("drm/amdgpu/vcn2.5: fix the enc loop with hw fini") |
| 14f43e8f88c5 ("drm/amdgpu: move JPEG2.5 out from VCN2.5") |
| b0f3cd3191cd ("drm/amdgpu: remove unnecessary JPEG2.0 code from VCN2.0") |
| 6ac27241106b ("drm/amdgpu: add JPEG v2.0 function supports") |
