| 955a67f79a97 ("clk: imx7up: Rename the clks to hws") |
| ea6a723a21f7 ("clk: imx: Rename the imx_clk_divider_gate to imply it's clk_hw based") |
| 40ad61d6b4e6 ("clk: imx: Rename the imx_clk_pfdv2 to imply it's clk_hw based") |
| 74e639519166 ("clk: imx: Rename the imx_clk_pllv4 to imply it's clk_hw based") |
| 7c3f951a9717 ("clk: imx: imx7ulp composite: Rename to show is clk_hw based") |
| c13f370d492d ("clk: imx7ulp: Fix watchdog2 clock name typo") |
| 72b2429d40d8 ("clk: imx7ulp: do not export out IMX7ULP_CLK_MIPI_PLL clock") |
| 2e2b928a04bd ("clk: imx7ulp: Correct DDR clock mux options") |
| 96ac93a7c4be ("clk: imx7ulp: Correct system clock source option #7") |
