blob: 1c51afbd9c8becbab3340cb9d39298bb702e9918 [file] [log] [blame]
a7480c5d725c ("irqchip/sifive-plic: Fix broken irq_set_affinity() callback")
f1ad1133b18f ("irqchip/sifive-plic: Add support for multiple PLICs")
ccbe80bad571 ("irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offline")
6a1ce99dc4bd ("RISC-V: Don't enable all interrupts in trap_init()")
a4c3733d32a7 ("riscv: abstract out CSR names for supervisor vs machine mode")